Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.

Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.

Abstract: An information handling system includes a printed circuit board, a screw, and a processor. The printed circuit board includes a through hole via. The through hole via includes top and bottom sections plated with a conductive plating material, and a middle section without any conductive plating material. The screw in physical communication with the top, middle, and bottom sections of the through hole via in the printed circuit board. The processor determines whether an electrical circuit is formed between the screw, the top section of the through hole via, and the bottom section of the through hole via. Based on the determination of the electrical circuit being formed, the processor provides an indication that no intrusion has been made into the information handling system.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A probe card and a manufacturing method of a probe card are provided. The probe card includes a probe head, first and second substrates, an insulating component, and an adhesive member. The second substrate is disposed between the probe head and the first substrate, and is disposed on the first substrate. The second substrate faces the first substrate and includes second contacts. The second contacts are electrically connected to first contacts of the first substrate. The insulating component is disposed between the first substrate and the second substrate, and disposed at an outer side of the second contacts. The adhesive member is disposed on the first substrate, arranged on at least a part of the side surface of the second substrate, and disposed at an outer side of the insulating component.

Abstract: The present disclosure provides a method for repairing a seam within a conformally deposited material. One or more seam repairing precursor sources may be delivered to seams or voids using a carrier at a super critical fluid phase. At the super critical fluid phase, the carrier has liquid like density and gas like high diffusion capability, therefore capable of delivering the repairing precursor sources to seams or voids under surfaces of a structure. In some embodiments, carbon dioxide or argon may be used as a carrier.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: A probe pin cleaning pad including a release layer or composite plate, an adhesive layer, a substrate layer, a cleaning layer, and a polishing layer is provided. The adhesive layer is disposed on the release layer or composite plate. The substrate layer is disposed on the adhesive layer. The cleaning layer is disposed on the substrate layer. The polishing layer is disposed on the cleaning layer. A cleaning method for a probe pin is also provided.

Abstract: A probe pin cleaning pad including a release layer or composite plate, an adhesive layer, a substrate layer, a cleaning layer, and a polishing layer is provided. The adhesive layer is disposed on the release layer or composite plate. The substrate layer is disposed on the adhesive layer. The cleaning layer is disposed on the substrate layer. The polishing layer is disposed on the cleaning layer. A cleaning method for a probe pin is also provided.

Abstract: A probe pin cleaning pad is provided, including a release layer or composite plate, an adhesive layer, a substrate layer, and a cleaning layer. The adhesive layer is disposed on the release layer or composite plate. The substrate layer is disposed on the adhesive layer. The cleaning layer is disposed on the substrate layer. A cleaning method for a probe pin is also provided.