Abstract: A method is described for testing the reliability of terminals in a semiconductor package proposes the placing of a test chip in the package, wherein the test chip has an insulating substrate, a conductive metal blanket layer on the substrate, a passivating layer over the metal layer provided with a plurality of openings, a plurality of Gold (Au) terminals in the openings bonded to the metal layer, and a master ground terminal bonded to the metal layer. Input/Output (I/O) terminals are provided in the package structure for each of the Au terminals, and master terminals are connected to the I/O terminals with wire, the test chip is sealed in the package. The resistance of each of the terminals is then monitored over a period of time to determine any change of electrical resistance, which is indicative of terminal deterioration.