Abstract: Aspects of the present disclosure provide a method and a system for providing a selection of golden tools for better defect density and product yield. A golden tool selection and dispatching system is provided to integrate different components for robust golden tool selection and dispatching. The golden tool selection system selects a set of golden tools based on performance of a set of manufacturing tools and provides a fully automated operational environment to produce a product using the set of golden tools.

Abstract: A via hole for a metal contact is formed by depositing a metal layer on the surface of a semiconductor device structure; depositing a thick PECVD oxide on the metal layer; patterning the metal layer using photolithography and etching so that what remains after this step is patterned metal regions such as lines or pads, each of which metal regions is covered by a thick PECVD oxide; creating islands of PECVD oxide using a photolithography process on the patterned metal regions at locations where it is desired to form via holes, the remainder of the patterned metal regions being covered with a thin PECVD oxide under layer; depositing a spin-on planarization material, such as SOG or low K polymer resulting in only a thin layer of spin-on material on top of the islands; using a partial etchback, removing the SOG from the top of the islands; depositing a PECVD oxide capping layer and polishing the capping layer using CMP; and then forming the via holes in the PECVD islands.

Abstract: A planarization process, featuring removal of spin on glass, used to fill narrow spaces between metal lines, has been developed. A dual dielectric, of underlying silicon oxide, and overlying silicon nitride, are initially used to passivate the metal lines, followed by the spin on glass fill. A RIE etchback of the spin on glass proceeds to a point in which the silicon nitride, on the metal line, is exposed. The exposed silicon nitride is then removed leaving a silicon oxide passivated metal line, and seamless insulator filled spaces. The ability of not exposing the passivating silicon oxide to RIE echback process, allows seamless fills to result.

Abstract: An improved structure and a process for forming an interlevel dielectric layer having a low capacitance between closely spaced metallurgy lines is provided. The method begins with a substrate surface having closely spaced metallurgy lines. A silicon oxide dielectric layer having a closed void between adjacent metallurgy lines is formed using electro cyclotron resonance techniques. The voids in the silicon dioxide dielectric layer are formed by controlling the ECR process parameters to achieve a proper etch to deposition ratio. The etch to deposition ratio of the silicon oxide layer is adjusted to the particular height and spacing between the metallurgy lines. Next, a spin-on-glass layer is formed over the silicon oxide dielectric layer. Portions of the SOG layer are etched back or chemically mechanically polished. The void (air) has a lower capacitance than the ECR silicon oxide layer.

Abstract: A method is described wherein topography of semiconductor wafer surfaces is improved. This is accomplished by introducing a specific planarization technique after the deposition of the first level of metal. It is shown further that the technique involves a combination of oxide and spin-on-glass layers. The resulting dielectric system is etched back in such a way that the resulting two-tiered metal-oxide structure and the surface thereover offers a uniformly flat depth-of-field which in turn makes possible the use of submicron optolithographic tools for the ultra high density integrated circuit chips. In an attempt to improve further the required flatness for submicron technologies, it is shown that silicon nitride may be introduced at a judiciously chosen process step so as to minimize the propagation of surface irregularities from one layer to another through minimizing the so-called microloading effect.

Abstract: A process for forming an planar dielectric layer over metallurgy lines using an in situ multi-step electron cyclotron resonance (ECR) oxide deposition process. A substrate with metallurgy lines on its surface is covered with a protective ECR oxide layer. The novel ECR process for the protective layer does not have an argon flow and does not etch the surface (e.g., metal lines) it is deposited upon. Next, a gap-fill step is formed over the protective layer. The gap-fill step uses Argon flow and rf power to enhance the deposition in gaps and the planarization. The gap-fill layer etches the underlying protective layer but the protective layer prevents the gap-fill deposition/etch process from attacking and damaging the metallurgy lines. Next, the protective layer and the gap-fill layer sequence are repeated until the desired thickness is obtained. A thick capping protective layer and a capping gap-fill layer are used to complete the planarization process.

Abstract: A gas discharge through nitrous oxide or nitrogen is used to remove polymeric deposits that form on the surface of a layer of a spin-on glass that was etched in an atmosphere of carbon-fluorine compounds. Removal of the polymeric deposit greatly improves adhesion to the spin-on glass layer of subsequently deposited layers. The removal is accomplished without increasing any tendency of the spin-on glass layer to absorb moisture.

Abstract: An improved process for planarization of an integrated circuit structure having raised portions is provided. A conformal insulating layer is deposited over the structure. Next, a sacrificial dielectric layer is formed over the insulating layer. A planarization layer is formed over the dielectric layer. Then, parts of the planarization layer, dielectric layer, and insulating layer are etched to planarize said integrated circuit structure using an etch chemistry which provides for an uniform etch rate through all three layers. The sacrificial dielectric layer and the etch chemistry provide uniform etching by eliminating micro loading effects.