Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a bump pad interconnect. The bump pad interconnect comprises a profile cross section that has a trapezoid shape. The integrated device is coupled to the substrate through the bump pad interconnect. The bump pad interconnect is located in a cavity of the at least one dielectric layer of the substrate.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

Abstract: Antenna modules employing a package substrate with a vertically-integrated patch antenna(s), and related fabrication methods. The antenna module includes a radiofrequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and an antenna(s) in the package substrate. The package substrate includes one or more patch antennas that are planar-shaped and vertically integrated in a plurality of metallization layers in the package substrate, behaving electromagnetically as a patch antenna. In this manner, the patch antenna(s) can be formed as a vertically-integrated structure in the package substrate with fabrication methods used for fabricating metal interconnects and vias (e.g., a micro via fabrication process) in package substrates.

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.

Abstract: Radio-frequency (RF) integrated circuit (IC) (RFIC) packages employing a substrate sidewall partial shield for electro-magnetic interference (EMI) shielding. A RFIC package includes an IC die layer that includes a RFIC die(s) mounted on a substrate that includes substrate metallization layers, a substrate core, and substrate antenna layers. The RFIC package includes an EMI shield surrounding the IC die layer and extending down shared sidewalls of the IC die layer and the substrate. The EMI shield extends down the sidewalls of the IC die layer and substrate metallization layers of the substrate to at least the interface between the substrate metallization layers and the substrate core, and without extending adjacent to the sidewall of the substrate antenna layers. In this manner, antenna performance of the antenna module may not be degraded, because extending the EMI shield down sidewalls of the substrate antenna layers can create a resonance cavity in the substrate.

Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a core layer comprising a first surface and a second surface; at least one first dielectric layer coupled to the first surface of the core layer; at least one second dielectric layer coupled to the second surface of the core layer; at least one core interconnect that extends through the core layer and at least one dielectric layer from the at least first dielectric layer and/or the at least one second dielectric layer; a plurality of high-density interconnects comprising a first minimum width and a first minimum spacing; and a plurality of interconnects comprising a second minimum width and a second minimum spacing. The second minimum width is greater than the first minimum width. The second minimum spacing is greater than the first minimum spacing.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.

Abstract: Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (?m)/5.0 ?m or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.

Abstract: Certain aspects of the present disclosure provide an asymmetric antenna structure. An example antenna device generally includes a first antenna element, a second antenna element, and a flexible coupling element asymmetrically positioned between surfaces of the first and second antenna elements and electrically coupling the first antenna element to the second antenna element.

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.

Abstract: Radio-frequency (RF) integrated circuit (IC) (RFIC) packages employing a substrate sidewall partial shield for electro-magnetic interference (EMI) shielding. A RFIC package includes an IC die layer that includes a RFIC die(s) mounted on a substrate that includes substrate metallization layers, a substrate core, and substrate antenna layers. The RFIC package includes an EMI shield surrounding the IC die layer and extending down shared sidewalls of the IC die layer and the substrate. The EMI shield extends down the sidewalls of the IC die layer and substrate metallization layers of the substrate to at least the interface between the substrate metallization layers and the substrate core, and without extending adjacent to the sidewall of the substrate antenna layers. In this manner, antenna performance of the antenna module may not be degraded, because extending the EMI shield down sidewalls of the substrate antenna layers can create a resonance cavity in the substrate.

Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.

Abstract: Methods and apparatuses for enhancing antenna modules with a shield layer. The apparatus includes an antenna module having an antenna layer. The antenna layer includes an antenna. The antenna module further includes a signal routing layer; a radio frequency (RF) communication component disposed on the signal routing layer; a shield cover encasing the RF communication component; and a shield layer. The antenna module further includes an antenna module side. The antenna module side includes a side of the signal routing layer and a side of the antenna layer. The shield layer covers a portion of the antenna module side such that at least a portion of the side of the antenna layer is uncovered.

Abstract: A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.

Abstract: Methods and apparatuses for enhancing antenna modules with a shield layer. The apparatus includes an antenna module having an antenna layer. The antenna layer includes an antenna. The antenna module further includes a signal routing layer; a radio frequency (RF) communication component disposed on the signal routing layer; a shield cover encasing the RF communication component; and a shield layer. The antenna module further includes an antenna module side. The antenna module side includes a side of the signal routing layer and a side of the antenna layer. The shield layer covers a portion of the antenna module side such that at least a portion of the side of the antenna layer is uncovered.

Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body, wherein the dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell having a structure in which titanium is partially substituted with an element having the same oxidation number as that of the titanium in the barium titanate-based powder particle and having an ionic radius different from that of the titanium in the barium titanate-based powder particle, and the shell covers at least 30% of a surface of the core.