Patents by Inventor Chin-Lan Tseng

Chin-Lan Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8507987
    Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 13, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
  • Publication number: 20110068415
    Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 24, 2011
    Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
  • Publication number: 20100109080
    Abstract: A pseudo-drain MOS transistor is disclosed. The transistor includes a semiconductor substrate; a gate structure disposed on the semiconductor substrate; a source, a pseudo-drain, a drain, and a shallow trench isolation disposed in the semiconductor substrate, a p-well disposed in the semiconductor substrate and under the source and the gate structure; and an n-well disposed under the drain. The source and the pseudo-drain are disposed adjacent to two sides of the gate structure and the shallow trench isolation is disposed between the pseudo-drain and the drain, and the n-well is extended toward the pseudo-drain while not reaching the area below the gate structure.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 6, 2010
    Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
  • Publication number: 20080251863
    Abstract: A high-voltage RF power device includes a plurality of serially connected transistors. Each transistor includes a gate finger disposed on a substrate, a gate dielectric layer, a drain structure disposed on one side of the gate finger, and an N+ source region on the other side of the gate finger. The drain structure includes an N+ doping region encompassed by a shallow trench isolation (STI) structure, and an N well directly underneath the STI structure and the N+ doping region.
    Type: Application
    Filed: April 14, 2007
    Publication date: October 16, 2008
    Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Yu-Chia Chen, Chin-Lan Tseng, Chih-Yuh Tzeng, Victor-Chiang Liang, Chun-Yi Lin