Patents by Inventor Chin Liu
Chin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
METHOD AND SYSTEM FOR CALCULATING PARAMETERS IN LARYNX IMAGE WITH ARTIFICIAL INTELLIGENCE ASSISTANCE
Publication number: 20240169533Abstract: A method for calculating parameters in a larynx image with an artificial intelligence assistance includes training a deep learning object detection software and a deep learning image recognition and segmentation software to extract a glottis image from a larynx image and recognize a membranous glottal gap; after receiving a larynx image, a plurality of larynx images captured frame-by-frame, or a larynx video that is captured when vocal folds are in a phonating state, extracting a glottis image by the deep learning object detection software; recognizing a membranous glottal gap in the glottis image and correspondingly outputting a membranous glottal gap filter by the deep learning image recognition and segmentation software; performing image processing of edge detection and image patching on the membranous glottal gap filter to clearly outline the membranous glottal gap and obtaining a medical parameter of several vocal fold anatomies from the clearly outlined membranous glottal gap.Type: ApplicationFiled: November 17, 2023Publication date: May 23, 2024Applicant: Changhua Christian Medical Foundation Changhua Christian HospitalInventors: ANDY CHEN, ACQUAH HACKMAN, MU-KUAN CHEN, CHIH-CHIN LIU -
Patent number: 11987431Abstract: A top-opening substrate carrier comprises a container body, a door member and at least one latching mechanism. The latching mechanism includes a rotary drive member, a first driven cam, a second driven cam, a first connecting rod, a second connecting rod, two longitudinal latching arms and two lateral latching arms. The first driven cam and the second driven cam are disposed at two sides of the rotary drive member. When the rotary drive member is rotated by force, it links and activates the first connecting rod and the second connecting rod to synchronously drive the first driven cam and the second driven cam to rotate, thereby driving the two longitudinal latching arms and the two lateral latching arms to project towards locking holes of the container body and locked, or retract from the locking holes of the container body and unlocked.Type: GrantFiled: March 27, 2023Date of Patent: May 21, 2024Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.Inventors: Ming-Chien Chiu, Yung-Chin Pan, Cheng-En Chung, Chih-Ming Lin, Po-Ting Lee, Wei-Chien Liu, Tzu-Ning Huang
-
Publication number: 20240157285Abstract: A system and method are provided for capturing carbon dioxide from a flue gas. The system includes an absorber, a stripper, a cooling system and a control module. The cooling system is adapted to independently cool (a) a flue gas upstream from an absorber flue gas inlet and (b) a carbon dioxide-lean carbon capture solution being delivered to each of a plurality of lean carbon capture solution inlets at the different levels of the absorber. The control module includes a controller and a plurality of temperature sensors. The controller is responsive to the plurality of temperature sensors provided at each of the different levels of the absorber to control operation of the cooling system and thereby maintain a desired temperature profile at the different levels of the absorber to enhance rich loading of carbon dioxide from the flue gas to a carbon capture solution and reduce energy requirements for lean carbon capture solution regeneration in the stripper.Type: ApplicationFiled: November 14, 2023Publication date: May 16, 2024Inventors: Kunlei Liu, Heather Nikolic, Reynolds Frimpong, Fan Zhen, Chin Ng
-
Publication number: 20240164003Abstract: An electrostatic discharge device including at least two conductive materials isolated from each other and at least one electrostatic eliminator. The conductive materials are located outside two opposite side walls of an insulated fluid-carrying member and separated from the side walls thereof. When electrostatic charges are accumulated on the insulated fluid-carrying member, the electrostatic charges form an electrostatic voltage on the conductive materials. The electrostatic eliminator is electrically connected to the conductive materials and directly disconnected from a grounding terminal. The electrostatic eliminator releases and eliminates the electrostatic charges by the conductive materials to reduce the electrostatic voltage. In addition, the insulated fluid-carrying member can also be replaced by an insulation container. When the insulation container is used, induction electrodes can replace the conductive materials in the insulation container.Type: ApplicationFiled: November 16, 2023Publication date: May 16, 2024Inventors: TAO-CHIN WEI, YUAN-PING LIU, YI-CHENG LIU
-
Publication number: 20240147718Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
-
Publication number: 20240134968Abstract: An electronic system and a security authority delegation method thereof are provided. The electronic system includes a first host device, a second host device, a first security device, and a second security device. The first security device is connected to the first host device. The second security device is connected to the second host device and the first security device. The first security device performs an attestation process on the second security device. If the second security device passes the attestation process, the first security device enables the second security device to verify executable images of the second host device. If the second security device does not pass the attestation process, the first security device disables a function of the second security device, and the function includes verifying the executable image of the second host device.Type: ApplicationFiled: December 15, 2022Publication date: April 25, 2024Applicant: ASPEED Technology Inc.Inventors: Chin-Ting Kuo, Chia-Wei Wang, Hung Liu
-
Patent number: 11967446Abstract: An inductor is disclosed, the inductor comprising: a T-shaped magnetic core, being made of a material comprising an annealed soft magnetic metal material and having a base and a pillar integrally formed with the base, wherein ?C×Hsat?1800, where ?C is a permeability of the T-shaped magnetic core, and Hsat (Oe) is a strength of the magnetic field at 80% of ?C0, where ?C0 is the permeability of the T-shaped magnetic core when the strength of the magnetic field is 0.Type: GrantFiled: January 4, 2021Date of Patent: April 23, 2024Assignee: CYNTEC CO., LTD.Inventors: Chun-Tiao Liu, Lan-Chin Hsieh, Tsung-Chan Wu, Chi-Hsun Lee, Chih-Siang Chuang
-
Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
-
Patent number: 11941298Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.Type: GrantFiled: April 19, 2022Date of Patent: March 26, 2024Assignee: MediaTek Inc.Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Chin Chin Cheng, Szu-Chi Liu
-
Publication number: 20240093364Abstract: A defect-reducing coating method is disclosed, which is characterized by making the coating surface of a sample face the bottom of the coating chamber, so that the sticking particles on side walls of the coating chamber will not fall on the coating surface of the sample during the coating process, thereby a smooth coating layer can be formed on the coating surface of the sample after the coating process is finished.Type: ApplicationFiled: November 21, 2022Publication date: March 21, 2024Applicant: MSSCORPS CO., LTD.Inventors: CHI-LUN LIU, JUNG-CHIN CHEN, BANG-HAO HUANG, YU-HAN CHEN, LIKO HSU
-
Publication number: 20240087947Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.Type: ApplicationFiled: January 10, 2023Publication date: March 14, 2024Inventors: Chung-Ting Ko, Yu-Cheng Shiau, Li-Jung Kuo, Sung-En Lin, Kuo-Chin Liu
-
Publication number: 20240055527Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.Type: ApplicationFiled: October 25, 2023Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
-
Patent number: 11895836Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.Type: GrantFiled: September 16, 2020Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
-
Patent number: 11830948Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.Type: GrantFiled: September 14, 2020Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
-
Publication number: 20230369334Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Duen-Huei Hou, Tsu Hao Wang, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu
-
Patent number: 11749681Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.Type: GrantFiled: March 9, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Duen-Huei Hou, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu, J. H. Wang
-
Patent number: 11745050Abstract: A positioning device for a portable fitness equipment mainly provides a support frame for hanging the portable fitness equipment. The support frame includes a base and a support rod connected to each other, and there is an obtuse angle between the base and the support rod. The obtuse angle design allows the position where the support rod is connected to the base to bear less torque, which can effectively prevent the support rod from shaking or damage; and the portable fitness equipment can slide or can be fixed on the support rod, allowing users to adjust the portable fitness equipment to the most suitable height.Type: GrantFiled: July 23, 2021Date of Patent: September 5, 2023Assignee: C2P (Taiwan) Ltd.Inventor: Chin-Liu Wang
-
Patent number: 11714357Abstract: A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.Type: GrantFiled: June 30, 2021Date of Patent: August 1, 2023Assignee: ASML NETHERLANDS B.V.Inventors: Alexander Ypma, Cyrus Emil Tabery, Simon Hendrik Celine Van Gorp, Chenxi Lin, Dag Sonntag, Hakki Ergün Cekli, Ruben Alvarez Sanchez, Shih-Chin Liu, Simon Philip Spencer Hastings, Boris Menchtchikov, Christiaan Theodoor De Ruiter, Peter Ten Berge, Michael James Lercel, Wei Duan, Pierre-Yves Jerome Yvan Guittet
-
Publication number: 20230235148Abstract: Disclosed herein is a method for decolorizing a colored polymer material, which includes subjecting the colored polymer material to a first decolorizing treatment with a first decolorizing solution to remove a colorant from the colored polymer material, so as to obtain a first decolorized polymer material and a first used decolorizing solution. A method for preparing a regenerated polymer, and a decolorizing solution are also disclosed.Type: ApplicationFiled: August 16, 2022Publication date: July 27, 2023Inventors: Jia-Ying WU, Ruey-Fen LIAO, Pang-Chin LIU
-
Publication number: 20230167100Abstract: The invention disclosed herein relates to aza-quinoline compounds of Formula (I), pharmaceutical compositions comprising such compounds, and the use of such compounds for treating a disease or condition mediated by Enhancer of Zeste Homolog 2 (EZH2), Polycomb Repressive Complex 2 (PRC2), or a combination thereof.Type: ApplicationFiled: August 10, 2021Publication date: June 1, 2023Inventors: Xuan DAI, Michael DORE, Xiang-Ju Justin GU, Ling LI, Kun Chin LIU, Sing Yeung Frankie MAK, Yuan MI, Counde OYANG, Julien PAPILLON, Wei (Vicky) QI, Xiaoxia YAN, Zhengtian YU, Ji Yue (Jeff) ZHANG, Kehao ZHAO