Abstract: Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit position. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.

Abstract: An apparatus and method is discussed using a parity check matrix in order to acheive correction and detection of errors particularly pertaining to detection data fetched from a wrong address. The code structure enhances utilization of chip reliability by encoding and decoding digital signals through the utilization of a parity check matrix and parity bits generated from system address bits of a computer system with k symbols and b bits per symbol.

Abstract: A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.

Abstract: Advantage is taken of the presence of identity submatrices in a parity check matrix to achieve correction of errors in a single symbol and detection of errors in a single symbol together with a single bit error in another symbol for use in computer memory systems. The code structure enhances utilization of chip real estate and specifically provides for the utilization of a (76,64) code which employs 19 chips per computer memory word as opposed to 20 chips per word.

Abstract: BCH error correcting code principles are employed in conjunction with normal basis representation of field elements to provide apparatus and method for encoding and decoding binary electrical signals in a way which ensures the ability to correct all double-bit errors and to detect all triple-bit errors. Both the encoder and decoder are designed in a fashion which permits modular implementation so as to make the circuits more compact and easier to layout.

Abstract: A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.

Abstract: A method is provided for the construction of systematic error correction codes having double symbol error detection and single symbol correction capabilities. These systematic codes are employed in conjunction with digital memory systems in which the same electrical circuit mechanism is employed for check bit generation and syndrome generation. As a result, the number of circuit levels is reduced, the circuit operates faster, and yet at the same time efficiencies of space or chip "real estate" utilization are achieved since fewer circuits are required to achieve the same objectives, especially with respect to encoding and syndrome generation.

Abstract: A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which is tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit positions. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.

Abstract: Byte or symbol organized linear block codes are optimized in terms of reducing the number of ones in their parity check matrices by means of symbol column transformations carried out by multiplication by non-singular matrices. Each optimized symbol column preferably, and probably necessarily, includes a submatrix which is the identity matrix which contributes to low weight check matrices and also to simplified decoding procedures and apparatus. Since circuit cost and layout area are proportional to the number of Exclusive-OR gates which is determined by the number of ones in the check matrix, it is seen that the reduction procedures carried out in accordance with the present invention solve significant problems that are particularly applicable in the utilization of byte organized semiconductor memory systems. Reduced weight coding systems are also generated in accordance with weight reducing procedures used in conjunction with modified Reed Solomon codes.

Abstract: A memory system that provides extra data bits without utilizing storage capacity. A first data word is fetched from memory and corrected to remove any single-bit errors. A second data word (which is a subset of the first data word as corrected) is then fetched, and new data correction bits (parity or ECC check bits) is generated for the second data word. Both the second data word and the newly-generated data correction bits are output. This structure amortizes the expense of in-system data correction over a greater data output, and over a smaller storage capacity relative to the data output.

Abstract: A barcode scanner, which is particularly suitable for reading barcode information from surfaces having various reflective properties, includes a light intensity control for the light source of the barcode scanner. The light intensity control preferably comprises a means for ramping voltage and a summing circuit which allows the current flowing through the light source to be controlled. In addition, the light intensity control utilizes a clocking means which controls the rate of voltage ramping.

Abstract: A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.

Abstract: A method for encoding and decoding signals in accordance with a class of modular coding schemes is employed. Through a representation of Galois field elements in terms of a normal basis, wherein subsequent basis entries are squares of previous entries, it is possible to construct quasi-cyclic codes capable of double error correction and triple error detection. Modularity is achieved both at the time of check bit generation and also at the time of syndrome generation. Moreover, this achievement is carried out so as to be applicable in the domain of double error correction codes. The code avoids duplication of circuitry and is efficient in terms of delay through logic gate levels. The code also provides the capability of having byte parity check indications which are helpful for isolating failures.

Abstract: A method and apparatus reliably and robustly decode single width bar codes that may be placed on a variety of materials. The decoding is independent of whether or not the bar code represents dark bars on a light background or light bars on a dark background. The decoder may be implemented either in hardware or as part of a program in a stored program general purpose computer. The signal processing approach taken generates gap sequence information from width sequence information to match predetermined gap sequence patterns. The method and apparatus of the present invention are also particularly amenable to independent creation of the gap sequences from three different techniques which are independent and which thus add robustness to the system. Lastly, the decoding method of the present invention takes advantage of a preprocessing function to remove any certain forms of noise that may be present in the scanned data.

Abstract: A method for encoding and decoding signals in accordance with a class of modular coding schemes is employed. Through a representation of Galois field elements in terms of a normal basis, wherein subsequent basis entries are squares of previous entries, it is possible to construct quasi-cyclic codes capable of double error correction and triple error detection. Modularity is achieved both at the time of check bit generation and also at the time of syndrome generation. Moreover, this achievement is carried out so as to be applicable in the domain of double error correction codes. The code avoids duplication of circuitry and is efficient in terms of delay through logic gate levels. The code also provides the capability of having byte parity check indications which are helpful for isolating failures.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: A method and apparatus is provided for producing single width barcodes in a continuous, serpentine pattern. This pattern provides continuity of operation for laser marking instruments and thereby results in the formation of more uniform and higher quality barcode indicia. The use of a continuous serpentine pattern also increases the speed at which the code may be written onto a substrate. This marking method is particularly appropriate for use in marking a wide variety of materials including semiconductors, metals, plastics and ceramics.

Abstract: In accordance with a preferred embodiment of the present invention, a mechanism is provided for converting Type II binary parity check matrices for a large class of codes into a larger parity check matrix which is more suitable for error detection and correction in memory systems which employ multiple bit per chip output architecture. More particularly, the present coding method provides codes which exhibit check bit requirements which are less than those for a Type II code but greater than those for a Type I code. In particular, the codes of the present invention are capable of detecting all combinations of a single symbol error and a single bit error. In addition, the codes for the present invention exhibit all of the correction and detection properties for a Type I code but do not rise to the capabilities or the complexities of Type II codes which are capable of correcting all single symbol errors and detecting all double symbol errors.