Patents by Inventor Chin-Shan Hou
Chin-Shan Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240139262Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.Type: ApplicationFiled: October 13, 2023Publication date: May 2, 2024Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
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Patent number: 9995998Abstract: A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.Type: GrantFiled: June 21, 2016Date of Patent: June 12, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shan Hou, Yu-Bey Wu
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Publication number: 20160370698Abstract: A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.Type: ApplicationFiled: June 21, 2016Publication date: December 22, 2016Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shan Hou, Yu-Bey Wu
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Patent number: 9377680Abstract: Provided is an integrated circuit (IC) testline layout. The layout has a device boundary and a main pattern boundary inside the device boundary. The layout includes at least one main pattern inside the main pattern boundary. The layout further includes a plurality of dummy patterns in a region that is between the main pattern boundary and the device boundary. The plurality of dummy patterns is printable in a photolithography process and is arranged in a ring with a uniform spacing between two adjacent dummy patterns.Type: GrantFiled: November 15, 2013Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shan Hou, Yu-Bey Wu
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Patent number: 9111768Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.Type: GrantFiled: September 15, 2014Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yu Lu, Shyue-Shyh Lin, Chin-Shan Hou, Kuo-Feng Yu, Tung-Heng Hsieh, Chih-Hung Wang, Jian-Hao Chen
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Patent number: 9070624Abstract: A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.Type: GrantFiled: December 16, 2011Date of Patent: June 30, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hao Chen, Chia-Yu Lu, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Hsien-Chin Lin, Shyue-Shyh Lin
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Publication number: 20150001678Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.Type: ApplicationFiled: September 15, 2014Publication date: January 1, 2015Inventors: Chia-Yu Lu, Shyue-Shyh Lin, Chin-Shan Hou, Kuo-Feng Yu, Tung-Heng Hsieh, Chih-Hung Wang, Jian-Hao Chen
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Patent number: 8859386Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.Type: GrantFiled: June 8, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yu Lu, Jian-Hao Chen, Chih-Hung Wang, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Shyue-Shyh Lin
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Publication number: 20130328131Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.Type: ApplicationFiled: June 8, 2012Publication date: December 12, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Yu Lu, Jian-Hao Chen, Chih-Hung Wang, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Shyue-Shyh Lin
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Publication number: 20130157452Abstract: A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC")Inventors: Jian-Hao Chen, Chia-Yu Lu, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Hsien-Chin Lin, Shyue-Shyh Lin
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Publication number: 20100090751Abstract: An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.Type: ApplicationFiled: December 14, 2009Publication date: April 15, 2010Inventors: Hsin-Li Cheng, Chia-Jung Lee, Chin-Shan Hou, Wei-Ming Chen
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Patent number: 7642176Abstract: An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.Type: GrantFiled: April 21, 2008Date of Patent: January 5, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Li Cheng, Chia-Jung Lee, Chin-Shan Hou, Wei-Ming Chen
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Publication number: 20090261450Abstract: An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.Type: ApplicationFiled: April 21, 2008Publication date: October 22, 2009Inventors: Hsin-Li Cheng, Chia-Jung Lee, Chin-Shan Hou, Wei-Ming Chen
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Patent number: 7155686Abstract: A new method to optimize a signal routing in an integrated circuit is achieved. The method comprises providing a signal routing in an integrated circuit layout. The signal routing comprises a configuration of metal lines in a stack of metal levels. Each metal level is separated from an underlying substrate by dielectric material. A Joule heating estimate is calculated for the signal routing. The Joule heating estimate is compared to a standard value. The signal routing is updated if the Joule heating estimate exceeds the standard value. The updating comprises generating a new configuration of the metal lines in the metal levels. The new configuration reduces the Joule heating. The steps of calculating, comparing, and updating are repeated if the Joule heating estimate still exceeds the standard value. Joule heating is reduced by either routing on lower metal levels or by coupling the signal routing to a heat sink.Type: GrantFiled: March 9, 2004Date of Patent: December 26, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Shan Hou, Tong-Chern Ong, Jui-Ling Yang, Jun-Yi Wu
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Publication number: 20050258505Abstract: A programmable fuse device includes a polysilicon layer having a mixed ion implantation disposed on a silicon substrate. The polysilicon layer includes at least one first region having a first type ion implantation and at least one second region having a second type ion implantation opposite to the first type. Each of the first and second regions are disposed adjacently to form a corresponding polysilicon junction having a junction resistance. A silicide layer is disposed on the polysilicon layer. A predefined voltage potential is applied across the silicide layer for programming the device. This causes a flow of current through the silicide layer, which generates sufficient heat to cause an agglomeration in the silicide layer. The agglomeration causes at least one junction resistance to be included in series with the flow of current after the programming.Type: ApplicationFiled: May 20, 2004Publication date: November 24, 2005Inventors: Juing-Yi Wu, Tong-Chern Ong, Chin-Shan Hou
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Publication number: 20050204314Abstract: A new method to optimize a signal routing in an integrated circuit is achieved. The method comprises providing a signal routing in an integrated circuit layout. The signal routing comprises a configuration of metal lines in a stack of metal levels. Each metal level is separated from an underlying substrate by dielectric material. A Joule heating estimate is calculated for the signal routing. The Joule heating estimate is compared to a standard value. The signal routing is updated if the Joule heating estimate exceeds the standard value. The updating comprises generating a new configuration of the metal lines in the metal levels. The new configuration reduces the Joule heating. The steps of calculating, comparing, and updating are repeated if the Joule heating estimate still exceeds the standard value. Joule heating is reduced by either routing on lower metal levels or by coupling the signal routing to a heat sink.Type: ApplicationFiled: March 9, 2004Publication date: September 15, 2005Inventors: Chin-Shan Hou, Tong-Chern Ong, Jui-Ling Yang, Jun-Yi Wu
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Patent number: 6222221Abstract: A capacitor having a low voltage coefficient, even though one electrode is a semiconductor and one is a metal, is described. Two parallel plate capacitors are formed side by side and then cross-connected. The bottom plate of one of the capacitors is connected to the top plate of the other capacitor, and vice versa. This arrangement causes the two capacitors to be polarized in opposite directions at all times so that the individual voltage coefficients cancel each other and give the combined structure a value that is about 2 ppm V. A process for manufacturing this capacitor is also described.Type: GrantFiled: November 15, 1999Date of Patent: April 24, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chin-Shan Hou, Ming-Jer Chen
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Patent number: 6074905Abstract: A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate.Type: GrantFiled: December 28, 1998Date of Patent: June 13, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chu-Wei Hu, Chung-Te Lin, Chin-Shan Hou, Kuo-Hua Pan
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Patent number: 6069050Abstract: A capacitor having a low voltage coefficient, even though one electrode is a semiconductor and one is a metal, is described. Two parallel plate capacitors are formed side by side and then cross-connected. The bottom plate of one of the capacitors is connected to the top plate of the other capacitor, and vice versa. This arrangement causes the two capacitors to be polarized in opposite directions at all times so that the individual voltage coefficients cancel each other and give the combined structure a value that is about 2 ppm/V. A process for manufacturing this capacitor is also described.Type: GrantFiled: October 20, 1997Date of Patent: May 30, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chin-Shan Hou, Ming-Jer Chen
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Patent number: 6024887Abstract: A method for stripping an ion implanted photoresist layer from a substrate. There is first provided a substrate. There is then formed over the substrate an ion implanted photoresist layer. There is then treated the ion implated photoresist layer with a first plasma employing a first etchant gas composition comprising a fluorine containing species to form a fluorine plasma treated ion implanted photoresist layer. Finally, there is then stripped from the substrate the fluorine plasma treated ion implanted photoresist layer with a second plasma employing a second etchant gas composition comprising an oxygen containing species without the fluorine containing species. The ion implanted photoresist layer is stripped from the substrate without plasma induced damage to the substrate.Type: GrantFiled: June 3, 1997Date of Patent: February 15, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: So-Wen Kuo, Chin-Shan Hou, Yung Jung Chang