Patents by Inventor Chin-Shan Wang
Chin-Shan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180151570Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first transistor on the substrate, wherein the first transistor includes a first source/drain electrode. The semiconductor device further includes a second transistor on the substrate, wherein the second transistor includes a second source/drain electrode. The semiconductor device further includes an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode.Type: ApplicationFiled: January 26, 2018Publication date: May 31, 2018Inventors: Chin-Shan WANG, Shun-Yi LEE
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Publication number: 20180138168Abstract: A semiconductor device includes a substrate, source/drain contacts, gate structures, conductive elements, and a first stop layer. The substrate has source/drain regions formed therein. The source/drain contacts are over the substrate and each of the source/drain contacts is electrically connected to the respective source/drain region. The gate structures are arranged in parallel on the substrate. The source/drain regions are arranged at opposite sides of the gate structures. Each of the gate structures is sandwiched between two most adjacent source/drain contacts. The conductive element is on the source/drain contacts and crosses over the gate structures. The conductive element is overlapped with at least one gate structure and at least two most adjacent source/drain contacts and is electrically connected to the at least two most adjacent source/drain contacts.Type: ApplicationFiled: November 17, 2016Publication date: May 17, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Shan Wang, Shun-Yi Lee
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Patent number: 9893070Abstract: A method of fabricating a semiconductor device. The method includes forming a dummy structure over a substrate, forming conductive features on opposite sides of the dummy gate structure, removing the dummy structure and a portion of the substrate beneath the dummy gate structure to form a trench, and filling the trench with a dielectric material.Type: GrantFiled: June 10, 2016Date of Patent: February 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shan Wang, Shun-Yi Lee
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Publication number: 20180006017Abstract: A semiconductor device includes an interconnect layer on an inter-layer dielectric (ILD) structure. The ILD structure includes: first contacts, extending through the ILD structure, electrically connected to corresponding first components located in a floor structure underlying the ILD structure; at least one second component located within the ILD structure and spaced from a surface of the ILD structure (in a direction perpendicular to a plane of the ILD structure) a distance which is less than a thickness of the ILD structure; and second contacts directly contacting corresponding first regions of the at least one second component. The interconnect layer includes: first metallization segments which directly contact corresponding ones of the first contacts; and second metallization segments located over a second region of the at least one second component, a width of the second metallization segments being less than a width of the first metallization segments.Type: ApplicationFiled: September 2, 2016Publication date: January 4, 2018Inventors: Chin-Shan WANG, Shun-Yi LEE
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Publication number: 20170358584Abstract: A method of fabricating a semiconductor device. The method includes forming a dummy structure over a substrate, forming conductive features on opposite sides of the dummy gate structure, removing the dummy structure and a portion of the substrate beneath the dummy gate structure to form a trench, and filling the trench with a dielectric material.Type: ApplicationFiled: June 10, 2016Publication date: December 14, 2017Inventors: Chin-Shan WANG, Shun-Yi LEE
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Publication number: 20170345769Abstract: A method of fabricating a semiconductor structure. The method includes forming a dummy structure over a semiconductor body. The method further includes depositing an inter-layer dielectric (ILD) over the semiconductor body. The method further includes removing a dummy material of the dummy structure to form an opening in the ILD. The method further includes filling the opening with a dielectric material to form a dielectric structure. The method further includes stacking a plurality of interconnect elements over the dielectric structure.Type: ApplicationFiled: September 2, 2016Publication date: November 30, 2017Inventors: Chin-Shan WANG, Shun-Yi LEE
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Patent number: 9601373Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.Type: GrantFiled: May 3, 2016Date of Patent: March 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Shan Wang, Jian-Hong Lin, Shun-Yi Lee
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Publication number: 20160247721Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.Type: ApplicationFiled: May 3, 2016Publication date: August 25, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Shan WANG, Jian-Hong LIN, Shun-Yi LEE
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Patent number: 9425330Abstract: A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode.Type: GrantFiled: January 18, 2013Date of Patent: August 23, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shan Wang, Jian-Hong Lin, Chien-Jung Wang
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Patent number: 9356016Abstract: A semiconductor device includes a semiconductor substrate, a transistor, a conductive contact and a capacitor. The transistor is formed on the semiconductor substrate, and the transistor includes a gate, a source and a drain. The conductive contact is formed on and in contact with at least one of the source and the drain. The capacitor includes a first electrode and a second electrode spaced apart from first electrode. At least one of the first and second electrodes extends on substantially the same level as the conductive contact or the gate. A method of forming the semiconductor device is provided as well.Type: GrantFiled: October 17, 2014Date of Patent: May 31, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Shan Wang, Jian-Hong Lin, Shun-Yi Lee
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Publication number: 20160111418Abstract: A semiconductor device includes a semiconductor substrate, a transistor, a conductive contact and a capacitor. The transistor is formed on the semiconductor substrate, and the transistor includes a gate, a source and a drain. The conductive contact is formed on and in contact with at least one of the source and the drain. The capacitor includes a first electrode and a second electrode spaced apart from first electrode. At least one of the first and second electrodes extends on substantially the same level as the conductive contact or the gate. A method of forming the semiconductor device is provided as well.Type: ApplicationFiled: October 17, 2014Publication date: April 21, 2016Inventors: Chin-Shan WANG, Jian-Hong LIN, Shun-Yi LEE
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Publication number: 20130127016Abstract: A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode.Type: ApplicationFiled: January 18, 2013Publication date: May 23, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shan WANG, Jian-Hong LIN, Chien-Jung WANG
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Patent number: 8379365Abstract: A capacitor includes the first electrode including the first conductive lines and vias. The first conductive lines on the same layer are parallel to each other and connected to a first periphery conductive line. The first conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes a second electrode aligned opposite to the first electrode including second conductive lines and vias. The second conductive lines on the same layer are parallel to each other and connected to a second periphery conductive line. The second conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes oxide layers formed between the first electrode and the second electrode. The vias have rectangular (slot) shapes on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten.Type: GrantFiled: April 27, 2010Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Shan Wang, Jian-Hong Lin, Chien-Jung Wang
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Publication number: 20100271753Abstract: A capacitor includes the first electrode comprising the first conductive lines and vias, where the first conductive lines on the same layer are parallel to each other and connected to the first periphery conductive line, and the first conductor lines aligned in adjacent layers are coupled to each other by the vias; the second electrode aligned opposite to the first electrode comprising the second conductive lines and vias, where the second conductive lines on the same layer are parallel to each other and connected to the second periphery conductive line, and the second conductor lines aligned in adjacent layers are coupled to each other by the vias; and oxide layers formed between the first electrode and the second electrode, where the vias have rectangular (slot) shape on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten. The vias can have various sizes.Type: ApplicationFiled: April 27, 2010Publication date: October 28, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shan WANG, Jian-Hong LIN, Chien-Jung WANG