Patents by Inventor Chin-Sheng Chen
Chin-Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240167163Abstract: An anti-diffusion substrate structure includes a substrate, a substrate circuit layer, and a chip. The substrate has multiple through holes. Within each of the through holes includes a first metal layer and an anti-diffusion layer plated on the first metal layer. The anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer. The substrate circuit layer is mounted on the substrate and extended on the anti-diffusion layer within each of the through holes. The substrate circuit layer is made of a second metal layer, and a composition of the second metal layer is different from a composition of the first metal layer. The chip is electrically connected to the substrate circuit layer. The anti-diffusion layer is able to better prevent material of the first metal layer from migrating or diffusing to the second metal layer.Type: ApplicationFiled: December 23, 2022Publication date: May 23, 2024Inventors: YI LING CHEN, WEI TSE HO, CHIN-SHENG WANG, PU-JU LIN, CHENG-TA KO
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Patent number: 11989424Abstract: The invention discloses a digital signature system. The digital signature system comprises an electronic device and a data storage device. The electronic device generates a specific data by executing a specific operation, and calculates the specific data via a hash algorithm to generate a hash data. The data storage device comprises a controller, a plurality of flash memories, and a data transmission interface. The electronic device transmits the hash data to the data storage device via the transmission interface. The controller comprises a firmware. The firmware reads an unclonable function, and generates a private key according to the unclonable function, and encrypts the hash data by the private key to obtain a digital signature. The data storage device transmits the digital signature to the electronic device via the transmission interface.Type: GrantFiled: October 18, 2021Date of Patent: May 21, 2024Assignee: INNODISK CORPORATIONInventors: Ming-Sheng Chen, Chin-Chung Kuo
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Publication number: 20240130038Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.Type: ApplicationFiled: November 23, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Chin-Hsun WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Hung, Wei-Yu Liao, Chi-Min Chang
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Patent number: 11961637Abstract: This disclosure relates to a stretchable composite electrode and a fabricating method thereof, and particularly relates to a stretchable composite electrode including a silver nanowire layer and a flexible polymer film and a fabricating method thereof.Type: GrantFiled: December 7, 2022Date of Patent: April 16, 2024Assignee: TPK ADVANCED SOLUTIONS INC.Inventors: Wei Sheng Chen, Ching Mao Huang, Jia Hui Zhou, Huan Ran Yu, Shu Xiong Wang, Chin Hui Lee
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Publication number: 20240092415Abstract: An HOD device, comprising: a framework; covering material, covering the frame work; at least one conductive region, provided on or in the covering material; wherein the conductive region is coupled to a capacitance detection circuit or a predetermined voltage level. The HOD device can be a vehicle control device such as a steering wheel. The conductive region comprises conductive wires which can be threads of the covering material. By this way, the arrangements of the conductive wires can be changed corresponding to the size or the shape of the frame work or any other requirements. Also, the interference caused by unstable factors can be improved since the conductive wires can be coupled to a ground source of the vehicle to provide a short capacitance sensing path.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Applicant: PixArt Imaging Inc.Inventors: Chin-Hua Hu, Ching-Shun Chen, Yu-Han Chen, Yu-Sheng Lin
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Publication number: 20240087974Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11927312Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.Type: GrantFiled: April 18, 2022Date of Patent: March 12, 2024Assignee: Innolux CorporationInventors: Chin-Chia Huang, Chieh-Ying Chen, Jia-Huei Lin, Chin-Tai Hsu, Tzu-Chien Huang, Fu-Sheng Tsai
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Patent number: 11487924Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: GrantFiled: June 11, 2021Date of Patent: November 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
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Publication number: 20220309641Abstract: A system for analyzing image includes a data-acquiring module, a waveform-constructing module, a sampling module, a transforming module, and an analyzing module. The present system is utilized to retrieve normal data and real-time data, generate a normal waveform and a real-time waveform, sample normal sampling data from normal data and real-time sampling data from real-time data, transform first RGB values and second RGB values, and generate normal images and real-time images. The present system is utilized to detect whether a servo motor system is abnormal by analyzing real-time images with respect to normal images. In addition, a method of analyzing image is also provided.Type: ApplicationFiled: June 18, 2021Publication date: September 29, 2022Inventors: Chia-Jen LIN, Feng-Chieh LIN, Chun-Chi LAI, Chin-Sheng CHEN
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Publication number: 20220308099Abstract: A system for analyzing waveform, applied to a servo motor system, includes a data-acquiring module, a waveform-constructing module, a sampling module, a data-processing module, and a deep learning module. The present system retrieves normal data, abnormal date, and real-time data for generating a normal waveform, an abnormal waveform, and a real-time waveform, and then samples normal sampling data from the normal data, abnormal sampling data from the abnormal data, and real-time sampling data from the real-time data. The data-processing module is utilized to add the normal data and the abnormal data to form corresponding total data. The deep learning module utilizes a deep learning model to identify whether or not the real-time waveform is the normal waveform or the abnormal waveform by evaluating the normal waveform, the abnormal waveform and the total data.Type: ApplicationFiled: June 18, 2021Publication date: September 29, 2022Inventors: Chia-Jen LIN, Feng-Chieh LIN, Chun-Chi LAI, Chin-Sheng CHEN
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Publication number: 20210303765Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Inventors: CHIN-SHENG CHEN, CHING-YU CHAI, WEI-YI HU
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Patent number: 11048841Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: GrantFiled: May 15, 2020Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
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Publication number: 20200279063Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Inventors: CHIN-SHENG CHEN, CHING-YU CHAI, WEI-YI HU
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Patent number: 10678982Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: GrantFiled: October 29, 2018Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
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Publication number: 20190350715Abstract: A laminated structure with an adjustable elastic modulus has multiple connecting elements and at least one connecting point. Each connecting element is an S-shaped curved component, and has an inner end and an outer end. The multiple connecting elements are combined with each other by at least one connecting point, and a diameter of the at least one connecting point is equal to or greater than a diameter of each connecting element connected by the at least one connecting point.Type: ApplicationFiled: October 5, 2018Publication date: November 21, 2019Inventors: Yung-Lung Liu, Ralph Lee, Wen-Yi Chen, Chin-Sheng Chen, Royal Su, Zi-Xun Chen
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Publication number: 20190065647Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: ApplicationFiled: October 29, 2018Publication date: February 28, 2019Inventors: CHIN-SHENG CHEN, CHING-YU CHAI, WEI-YI HU
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Patent number: 10127338Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: GrantFiled: December 15, 2015Date of Patent: November 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Sheng Chen, Ching-Yu Chai, Wei-Yi Hu
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Patent number: 9996643Abstract: A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.Type: GrantFiled: November 17, 2014Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Sheng Chen, Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Ching-Shun Yang
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Publication number: 20170169146Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Inventors: CHIN-SHENG CHEN, CHING-YU CHAI, WEI-YI HU
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Patent number: 9572545Abstract: The present invention provides a radiotherapy system that can monitor a target location in real time. The radiotherapy system includes a remote control system operable to actuate a real-time image capturing device to acquire images in real time for monitoring the target location. The system also includes an image registration system that can register the acquired image with an image previously captured for the treatment plan, whereby it can be determined whether the patient's tumor is in the beam's eye view of the treatment plan. By confirming that the tumor is in the range of the beam's eye view, the accuracy of the treatment can be improved, and the irradiated area can be reduced, which makes the radiation treatment safer.Type: GrantFiled: May 8, 2012Date of Patent: February 21, 2017Assignees: Mackay Memorial Hospital, National Taipei University of TechnologyInventors: Yu-Jen Chen, Chia-Yuan Liu, Wen-Chung Chang, Chin-Sheng Chen