Patents by Inventor Chin-Yi Chiang
Chin-Yi Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10419567Abstract: A client terminal of an audio device redirection system includes: a storage device and a processor. The storage device stores a program code. When loaded and executed by the processor, the program code instructs the processor to perform the following steps: virtualizing an audio device of the client terminal as a virtual USB audio device on the client terminal; and redirecting the virtual USB audio device to a server terminal of the audio device redirection system for a virtual desktop infra-structure (VDI) service via a network interface based on a USB redirection protocol.Type: GrantFiled: March 21, 2017Date of Patent: September 17, 2019Assignee: ELITE SILICON TECHNOLOGY INC.Inventors: Tzu-Chiang Chiu, Chin-Yi Chiang
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Publication number: 20180278707Abstract: A client terminal of an audio device redirection system includes: a storage device and a processor. The storage device stores a program code. When loaded and executed by the processor, the program code instructs the processor to perform the following steps: virtualizing an audio device of the client terminal as a virtual USB audio device on the client terminal; and redirecting the virtual USB audio device to a server terminal of the audio device redirection system for a virtual desktop infra-structure (VDI) service via a network interface based on a USB redirection protocol.Type: ApplicationFiled: March 21, 2017Publication date: September 27, 2018Inventors: Tzu-Chiang Chiu, Chin-Yi Chiang
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Publication number: 20130050392Abstract: A surveillance system includes a controlling terminal and a remote-controlled terminal. The controlling terminal and the remote-controlled terminal are connected to a network and execute an identical instant messenger software. The remote-controlled terminal includes plural cameras serving as plural video sources of the instant messenger software. A first video source of the plural video sources is a selected video source. A controlling method for the surveillance system includes steps: (a) receiving a control message by the instant messenger software of the remote-controlled terminal, and (b) judging whether the control message is a specified control message, wherein if the control message is the specified control message, the selected video source is changed from the first video source to a second video source of the plural video sources according to the specified control message.Type: ApplicationFiled: February 21, 2012Publication date: February 28, 2013Applicant: Wishtek TechnologyInventor: Chin-Yi Chiang
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Patent number: 8194137Abstract: An image frame transmission method for use in a network transmission system is provided. The network transmission system includes an image sensor and an image processor. Firstly, a first image data segment of an image frame captured by the image sensor is outputted to the image processor in response to a first state of a control signal after an initial signal has been asserted by the image processor. Then, the output of a second image data segment of the image frame following the first image data segment to the image processor is delayed in response to the transition of the control signal from the first state to a second state. Afterward, the second image data segment is outputted to the image processor in response to the transition of the control signal from the second state to the first second state.Type: GrantFiled: February 2, 2005Date of Patent: June 5, 2012Assignee: Via Technologies, Inc.Inventors: Chin-Yi Chiang, Wallace Huang
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Patent number: 8055069Abstract: In a method for sampling image data from an image frame with component video, the image frame includes a first component frame, a second component frame and a third component frame. The method comprises steps of selecting a first component portion, a second component portion and a third component portion from the first component frame, the second component frame and the third component frame, respectively; and operating the first component portion, the second component portion and the third component portion to obtain a sampled unit arranged as a block array. The sampled unit includes at least a first component blocks derived from the first component portion, a second component block derived from the second component portion and a third component block derived from the third component portion.Type: GrantFiled: February 1, 2006Date of Patent: November 8, 2011Assignee: Via Technologies, Inc.Inventors: Chin-Yi Chiang, Wallace Huang, Giga Hsu
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Patent number: 7684650Abstract: In an image-frame processing method, the image frame is outputted from and image sensor by an image processor via the buffering of a memory buffer. The method includes the following steps of: defining at least two storage spaces in the memory buffer; dividing the image frame into a plurality of image portions, each of which has a size corresponding to the size of one of said at least two storage spaces; sequentially storing the image portions into the storage spaces in turn; and sequentially processing said image portions stored in the memory buffer. This method is applicable to processing the image frame with the use of a small-sized memory buffer.Type: GrantFiled: January 11, 2006Date of Patent: March 23, 2010Assignee: Via Technologies, Inc.Inventors: Chin-Yi Chiang, Wallace Huang
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Patent number: 7602975Abstract: A method and an apparatus for image compression. First, an image is partitioned into a plurality of image blocks, the image having A×B pixels, each of the image blocks having N×M pixels, wherein N is less than A and M is less than B. Next, a selected image block is outputted by selecting one of the image blocks as the selected image block. After that, a compressed image block is produced by storing the selected image block and compressing the selected image block. The step of outputting the selected image block and the step of producing the compressed image block are repeated until the image blocks are compressed into a plurality of compressed image blocks. Finally, a compressed image file is produced according to the compressed image blocks.Type: GrantFiled: December 8, 2005Date of Patent: October 13, 2009Assignee: Via Technologies, Inc.Inventors: Chin-Yi Chiang, Wallace Huang
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Patent number: 7596047Abstract: A memory card and a control chip capable of supporting various voltage supplies and a method of supporting voltages are discussed. The memory card includes a flash memory and a control chip for controlling the flash memory, and the control chip has a voltage regulator, a pad power supplier, a core controller and an output circuit. The voltage regulator transforms an external working voltage into a working voltage. The pad power supplier receives the external working voltage and adjusts a level of the external working voltage to output a pad working voltage according to an operating mode. The core controller receives the working voltage to work and generates a control signal. The output circuit receives the control signal and outputs a memory control signal according to a level of the pad working voltage. The control chip controls a flash memory with the memory control signal.Type: GrantFiled: July 10, 2006Date of Patent: September 29, 2009Assignee: Via Technologies, Inc.Inventors: Chin-Yi Chiang, Chien-Zhi Chen
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Patent number: 7487315Abstract: An accessing apparatus capable of reducing power consumption and an accessing method thereof are provided. The accessing method is applied in the accessing apparatus and a host. Firstly, the accessing apparatus is enabled to transmit an external data with the host according to an external clock, and transmit an internal data corresponding to the external data inside the accessing apparatus according to an internal clock. Next, the frequency of the external clock is detected. Then, the frequency of the internal clock is adjusted to a corresponding frequency according to the frequency of the external clock. Lastly, the internal data is transmitted between a buffer and a memory unit of the accessing apparatus by using an internal clock whose frequency equals the corresponding frequency.Type: GrantFiled: August 22, 2006Date of Patent: February 3, 2009Assignee: VIA Technologies, Inc.Inventors: Chin-Yi Chiang, Wallace Huang
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Patent number: 7352622Abstract: The disclosure relates to a data arranging method of a flash memory for improving access performance. The method includes steps of storing a first data sector to a page of the flash memory; storing a first data correction set corresponding to the first data sector in the page of the flash memory, wherein the first data correction set is next and contiguous to the first data sector; and repeating the two storing steps for storing a plurality of data sectors and a plurality of corresponding data correction sets until the page is formed.Type: GrantFiled: July 31, 2006Date of Patent: April 1, 2008Assignee: Via Technologies, Inc.Inventors: Chin-Yi Chiang, Tung-Chih Kuo, Chun-Hua Tseng, Yu-Wei Chang
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Patent number: 7254206Abstract: The invention is applied in a gigabit network environment. During the process of converting serial data into parallel data, a method is proposed to use the comma pattern in a data pipeline architecture to select word boundaries of a correct data frame from a serial bit stream. This method is further implemented in a bit receiver with a two-stage pipeline architecture to achieve the object of increasing data transmission bandwidth and efficiency.Type: GrantFiled: November 5, 2002Date of Patent: August 7, 2007Assignee: Via Technologies, Inc.Inventor: Chin-Yi Chiang
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Patent number: 7219846Abstract: A circuit module of a memory card is selectively used with card readers/writers compliant with different access protocols. The circuit module includes a shared non-volatile memory; a first transmission control unit communicable with a first card reader/writer for controlling data transmission from/to the first card reader/writer; a second transmission control unit communicable with a second card reader/writer for controlling data transmission from/to the second card reader/writer; and a data buffer and memory access controller coupled to the non-volatile memory and the first and second transmission control units for conducting a data transmission path between a designated transmission control unit and the non-volatile memory, thereby allowing data transmission between the designated card reader/writer and the non-volatile memory. The circuit module can be grouped with different carrier housings to produce a memory card kit.Type: GrantFiled: June 17, 2005Date of Patent: May 22, 2007Assignee: Via Technologies, Inc.Inventors: Jeffrey Kuo, Chin-Yi Chiang, Abel Lien, Wallace Huang
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Patent number: 7215578Abstract: A method for driving a flash memory and flash memory apparatus thereof are provided. The flash memory apparatus comprises a flash memory controller and a flash memory. At first, a voltage level of the parameter definition pin is detected by the flash memory controller to obtain the basic configuration of the flash memory when the flash memory controller is in a reset mode. Next, a fundamental access operation is performed on the flash memory by the flash memory controller according to the basic configuration. Then, a detail configuration is read from a specific data block of the flash memory. At last, the flash memory is driven according to the basic configuration and the detail configuration of the flash memory.Type: GrantFiled: January 19, 2006Date of Patent: May 8, 2007Assignee: Via Technology, Inc.Inventors: Chin-Yi Chiang, Chun-Hua Tseng
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Publication number: 20070061503Abstract: The disclosure relates to a data arranging method of a flash memory for improving access performance. The method includes steps of storing a first data sector to a page of the flash memory; storing a first data correction set corresponding to the first data sector in the page of the flash memory, wherein the first data correction set is next and contiguous to the first data sector; and repeating the two storing steps for storing a plurality of data sectors and a plurality of corresponding data correction sets until the page is formed.Type: ApplicationFiled: July 31, 2006Publication date: March 15, 2007Applicant: Via Technologies, Inc.Inventors: Chin-Yi Chiang, Tung-Chih Kuo, Chun-Hua Tseng, Yu-Wei Chang
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Publication number: 20070058477Abstract: An accessing apparatus capable of reducing power consumption and an accessing method thereof are provided. The accessing method is applied in the accessing apparatus and a host. Firstly, the accessing apparatus is enabled to transmit an external data with the host according to an external clock, and transmit an internal data corresponding to the external data inside the accessing apparatus according to an internal clock. Next, the frequency of the external clock is detected. Then, the frequency of the internal clock is adjusted to a corresponding frequency according to the frequency of the external clock. Lastly, the internal data is transmitted between a buffer and a memory unit of the accessing apparatus by using an internal clock whose frequency equals the corresponding frequency.Type: ApplicationFiled: August 22, 2006Publication date: March 15, 2007Applicant: VIA TECHNOLOGIES, INC.Inventors: Chin-Yi Chiang, Wallace Huang
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Publication number: 20070008801Abstract: A memory card and a control chip capable of supporting various voltage supplies and a method of supporting voltages thereof are provided. The memory card comprises a flash memory and a control chip for controlling the flash memory, and the control chip has a voltage regulator, a pad power supplier, a core controller and an output circuit. The voltage regulator transforms an external working voltage into a working voltage. The pad power supplier receives the external working voltage and adjusts a level of the external working voltage to output a pad working voltage according to an operating mode. The core controller receives the working voltage to work and generates a control signal. The output circuit receives the control signal and outputs a memory control signal according to a level of the pad working voltage. The control chip controls a flash memory with the memory control signal.Type: ApplicationFiled: July 10, 2006Publication date: January 11, 2007Applicant: VIA TECHNOLOGIES, INC.Inventors: Chin-Yi Chiang, Chien-Zhi Chen
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Publication number: 20060188149Abstract: In a method for sampling image data from an image frame with component video, the image frame includes a first component frame, a second component frame and a third component frame. The method comprises steps of selecting a first component portion, a second component portion and a third component portion from the first component frame, the second component frame and the third component frame, respectively; and operating the first component portion, the second component portion and the third component portion to obtain a sampled unit arranged as a block array. The sampled unit includes at least a first component blocks derived from the first component portion, a second component block derived from the second component portion and a third component block derived from the third component portion.Type: ApplicationFiled: February 1, 2006Publication date: August 24, 2006Inventors: Chin-Yi Chiang, Wallace Huang, Giga Hsu
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Publication number: 20060176741Abstract: A method for driving a flash memory and flash memory apparatus thereof are provided. The flash memory apparatus comprises a flash memory controller and a flash memory. At first, a voltage level of the parameter definition pin is detected by the flash memory controller to obtain the basic configuration of the flash memory when the flash memory controller is in a reset mode. Next, a fundamental access operation is performed on the flash memory by the flash memory controller according to the basic configuration. Then, a detail configuration is read from a specific data block of the flash memory. At last, the flash memory is driven according to the basic configuration and the detail configuration of the flash memory.Type: ApplicationFiled: January 19, 2006Publication date: August 10, 2006Inventors: Chin-Yi Chiang, Chun-Hua Tseng
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Publication number: 20060165297Abstract: A method and an apparatus for image compression. First, an image is partitioned into a plurality of image blocks, the image having A×B pixels, each of the image blocks having N×M pixels, wherein N is less than A and M is less than B. Next, a selected image block is outputted by selecting one of the image blocks as the selected image block. After that, a compressed image block is produced by storing the selected image block and compressing the selected image block. The step of outputting the selected image block and the step of producing the compressed image block are repeated until the image blocks are compressed into a plurality of compressed image blocks. Finally, a compressed image file is produced according to the compressed image blocks.Type: ApplicationFiled: December 8, 2005Publication date: July 27, 2006Inventors: Chin-Yi Chiang, Wallace Huang
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Publication number: 20060159349Abstract: In an image-frame processing method, the image frame is outputted from and image sensor by an image processor via the buffering of a memory buffer. The method includes the following steps of: defining at least two storage spaces in the memory buffer; dividing the image frame into a plurality of image portions, each of which has a size corresponding to the size of one of said at least two storage spaces; sequentially storing the image portions into the storage spaces in turn; and sequentially processing said image portions stored in the memory buffer. This method is applicable to processing the image frame with the use of a small-sized memory buffer.Type: ApplicationFiled: January 11, 2006Publication date: July 20, 2006Inventors: Chin-Yi Chiang, Wallace Huang