Abstract: A power-on reset (POR) circuit includes: a signal generator circuit for generating a first and a second signal according to an input voltage, and a comparator circuit. The comparator circuit, having a non-zero input offset, includes a first MOS transistor with a first conductive type and having a first conductive type gate and a first threshold voltage, and a second MOS transistor with a first conductive type and having a second conductive type gate and a second threshold voltage. The input offset relates to a difference between the first and the second threshold voltage. The first and the second signal control the first and the second MOS transistors respectively to generate a POR signal. When the input voltage exceeds a POR threshold which relates to a predetermined multiple or ratio of the input offset, the POR signal transits its state.

Abstract: A power-on reset (POR) circuit includes: a signal generator circuit for generating a first and a second signal according to an input voltage, and a comparator circuit. The comparator circuit, having a non-zero input offset, includes a first MOS transistor with a first conductive type and having a first conductive type gate and a first threshold voltage, and a second MOS transistor with a first conductive type and having a second conductive type gate and a second threshold voltage. The input offset relates to a difference between the first and the second threshold voltage. The first and the second signal control the first and the second MOS transistors respectively to generate a POR signal. When the input voltage exceeds a POR threshold which relates to a predetermined multiple or ratio of the input offset, the POR signal transits its state.

Abstract: A linear regulator circuit includes: a power switch having a first terminal coupled to an input voltage, a second terminal coupled to an output voltage, and a control terminal; an error amplifier, controlling the control terminal of the power switch according to a comparison between a feedback signal related to the output voltage and a reference signal; a first node, coupled between the error amplifier and the power switch; a transistor, coupled to the first node to provide a current path; and a body control unit, coupled between the input voltage and a body of the transistor, wherein when a change occurs in the input voltage, the body control unit controls a body voltage of the transistor to adjust a current in the current path, to correspondingly control a voltage of the first node, such that the control terminal of the power switch responds to the change.

Abstract: A linear regulator circuit includes: a power switch having a first terminal coupled to an input voltage, a second terminal coupled to an output voltage, and a control terminal; an error amplifier, controlling the control terminal of the power switch according to a comparison between a feedback signal related to the output voltage and a reference signal; a first node, coupled between the error amplifier and the power switch; a transistor, coupled to the first node to provide a current path; and a body control unit, coupled between the input voltage and a body of the transistor, wherein when a change occurs in the input voltage, the body control unit controls a body voltage of the transistor to adjust a current in the current path, to correspondingly control a voltage of the first node, such that the control terminal of the power switch responds to the change.

Abstract: The present invention discloses a fast-locked clock and data recovery circuit, which adopts a 2× oversampling technology and comprises: a multi phase-outputting phase-locked loop generating a plurality of phases ?i; a phase interpolator synthesizing the obtained phases ?n and ?n+2 into a sampling phase ?n based on the weighting coefficient k; a phase detector detects the phase lead or lag between the input data and the sampling phase and generates an up/down signal; and a phase search engine update the weighting coefficient and modulate the sampling phase according to the up/down correction signals. Further, the present invention proposes a data recovery circuit implementing a binary search method and a 2× oversampling method, whereby the time for clock locking can be greatly reduced. Furthermore, the present invention utilizes a multi-phase time-sharing parallel sampling technology to achieve high-speed operation and low power consumption.