Abstract: An apparatus and a method for performing an authenticated encryption with associated data (AEAD) operation of an encrypted instruction and a golden tag stored in a memory device in an event of a cache miss are provided. The apparatus includes a bus control circuit, a block buffer, a tag buffer and an AEAD circuit. The bus control circuit receives a read address from a cache for reading the encrypted instruction and the golden tag from the memory device. The block buffer receives and stores the encrypted instruction from the bus control circuit, wherein a size of the block buffer is preset to be N times a size of one cache line. The tag buffer receives and stores the golden tag from the bus control circuit. The AEAD circuit performs the AEAD operation upon the encrypted instruction and the golden tag to check whether the encrypted instruction is tampered or not.

Abstract: A drawer cart structure includes a first drawer trolley, a second drawer trolley, a plurality of drawers matching the first drawer trolley and the second drawer trolley, and a packaging box, wherein the drawers can be stacked separately into a first drawer set and a second drawer set according to the required number of drawers of the first drawer trolley and the second drawer trolley. The first drawer trolley and the second drawer trolley are in the form of open frame structures except for two sides and the top. The first drawer trolley and the second drawer trolley approach each other in opposite directions and from the bottoms of the two drawer trolleys, so that the first drawer trolley and the second drawer trolley are stacked crosswise and there is a distance between the tops of the first drawer trolley and the second drawer trolley.

Abstract: The present invention discloses a method of producing a medical implant adopting additive manufacturing including: distributing magnesium-zinc-zirconium alloy powder on a substrate to form a powder layer; generating a high-energy beam within a specific power range and directing the high-energy beam to the powder layer through a probe to sinter a region of the powder layer; distributing the plurality of magnesium-zinc-zirconium alloy powder on the sintered region of the powder layer; and repeating above steps until the medical implant is formed.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: The present disclosure discloses a simulating interface system, which is assembled with an electronic device and has an interface module and a simulating module. The interface module is connected with an external electronic device, and receives connection signals from the external electronic device; and the simulating module is connected with the interface module, and has a simulating unit and a management unit, wherein the simulating unit is used to simulate a use authority of the electronic device, and the management unit adjusts the use authority to provide to the external electronic device based on the connection signals. The simulating unit analogizes the use authority of the electronic device, and the management unit adjusts the use authority to provide to the external electronic device based on the connection signals from the external electronic device, so as to achieve effective protection.

Abstract: A functional resin material is manufactured by the following reagents including a polyol, a polyamine, a first cross-linking agent, a second cross-linking agent, and a nanocellulose. Each of the first cross-linking agent and the second cross-linking agent includes an isocyanate block.

Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Abstract: An integrated substation is provided. The integrated substation includes a cabinet and at least one airflow driver. The cabinet has a high pressure room, a low pressure room, and an exchange room located between the high pressure room and the low pressure room. The exchange room and the high pressure room are separated from each other by a first inner wall, and the exchange room and the low pressure room are separated from each other by a second inner wall.

Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

Abstract: A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.

Abstract: A secondary controller applied to a secondary side of a power converter includes a control signal generation circuit and a gate control signal generation circuit. The gate control signal generation circuit generates a gate control signal, and generates an injection signal according to the gate control signal. When a superposition voltage is less than a reference voltage, the control signal generation circuit generates a gate pulse control signal, wherein the gate pulse control signal corresponds to an output voltage of the power converter and the injection signal, the gate control signal generation circuit is further used for generating a gate pulse signal according to the gate pulse control signal, and the gate pulse signal is used for making a primary side of the power converter turned on.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.

Abstract: A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.

Abstract: The present disclosure provides a power assisted electric bicycle, a transmission device and a control method. The power assisted electric bicycle includes a body, a wheel, a torque sensor, a motor and a controller. The torque sensor is configured to output a plurality of torque signals corresponding to a pedal force. The controller is configured to: receive the torque signals from the torque sensor; compute and determine a first period according to a speed of the power assisted electric bicycle at a first time point; obtain a first maximum value of the torque signals in the first period that ends at the first time point; and, set a first torque output of the motor according to the first maximum value corresponding to the torque signal.

Abstract: An apparatus may include a heat pipe with a first portion residing in a first plane, a second portion residing in the first plane and a third portion positioned between the first portion and the second portion, the third portion residing in a second plane spaced-apart from the first plane. The apparatus further includes a base plate including an opening and a clip plate having a first region, a second region and a third region positioned between the first and the second regions. The third portion of the heat pipe is positioned within the opening, and the clip plate is coupled to the base plate such that i) the third region of the clip plate is in superimposition with the third portion of the heat pipe and ii) third region of the clip plate resides in the first plane.

Abstract: A method of reconstructing transcranial images using a dual-mode ultrasonic phased array includes steps of: controlling channels to emit energy toward an intracranial target point of a patient; respectively generating backscattered radiofrequency (RF) data by using the channels to receive backscattered energy reflected from the intracranial target; and reconstructing an acoustic distribution image based on those backscattered RF data in real-time. Compared with Pre-Treatment Ray Tracing Method, the present invention can display intracranial pressure distribution in real-time; compared with MR Thermometry, the present invention can be applied to low-energy applications without temperature change; and compared with Passive Cavitation Imaging, the present invention can stably present acoustic distribution images without relying on microbubbles.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.