Patents by Inventor Ching-Cheng Huang
Ching-Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080258305Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.Type: ApplicationFiled: April 7, 2008Publication date: October 23, 2008Applicant: MEGICA CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7413929Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.Type: GrantFiled: January 22, 2002Date of Patent: August 19, 2008Assignee: MEGICA CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Publication number: 20080188071Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.Type: ApplicationFiled: April 7, 2008Publication date: August 7, 2008Applicant: MEGIC CORPORATIONInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7397117Abstract: A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.Type: GrantFiled: November 24, 2004Date of Patent: July 8, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Publication number: 20080142978Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 2, 2008Publication date: June 19, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Publication number: 20080142979Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 18, 2008Publication date: June 19, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Publication number: 20080146019Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 2, 2008Publication date: June 19, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Patent number: 7388055Abstract: The invention relates to functional norbornenes as initiators for radical polymerization, its polymer and fabrication method thereof. More particularly, the functional norbornenes can be selectively polymerized by ring-opening metathesis polymerization or radical polymerization to obtain various polynorbornene derivatives or grafted copolymer materials. The polynorbornene derivatives and grafted copolymer materials not only exhibit excellent functional properties but also enhanced physical and chemical properties after modification. The polynorbornene derivatives and grafted copolymer materials disclosed in the invention exhibit excellent heat resistance, transparency and water resistance. The invention also deals with a process for producing such derivatives and materials having controllable molecular weight with narrow molecular weight distribution.Type: GrantFiled: March 22, 2007Date of Patent: June 17, 2008Assignee: National Taiwan University of Science & TechnologyInventors: Der-Jang Liaw, Ching-Cheng Huang, Jing-Yang Ju, Jiun-Tyng Liaw
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Publication number: 20080136034Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 18, 2008Publication date: June 12, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Publication number: 20080122099Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 2, 2008Publication date: May 29, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Publication number: 20080124918Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: February 2, 2008Publication date: May 29, 2008Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Publication number: 20080113504Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: October 31, 2007Publication date: May 15, 2008Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Publication number: 20080113503Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: October 31, 2007Publication date: May 15, 2008Applicant: MEGICA CORPORATIONInventors: Jin Yuan Lee, Ming Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Publication number: 20080111236Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: October 31, 2007Publication date: May 15, 2008Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Patent number: 7368508Abstract: The present invention relates to novel functional norbornenes as initiators for radical polymerization, its polymer and a process for producing the same. More particularly, the novel functional norbornenes can be selectively polymerized by ring-opening metathesis polymerization or radical polymerization to obtain various polynorbornene derivatives or grafted copolymer materials. The polynorbornene derivatives and grafted copolymer materials not only exhibit excellent functional properties but also enhanced physical and chemical properties after modification. The polynorbornene derivatives and grafted copolymer materials disclosed in the present invention exhibit excellent heat resistance, transparency and water resistance. The present invention also deals with a process for producing such derivatives and materials having controllable molecular weight with narrow molecular weight distribution.Type: GrantFiled: March 22, 2007Date of Patent: May 6, 2008Assignee: National Taiwan University of Science & TechnologyInventors: Der-Jang Liaw, Ching-Cheng Huang, Jing-Yang Ju, Jiun-Tyng Liaw
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Patent number: 7368509Abstract: The present invention relates to novel functional norbornenes as initiators for radical polymerization, its polymer and a process for producing the same. More particularly, the novel functional norbornenes can be selectively polymerized by ring-opening metathesis polymerization or radical polymerization to obtain various polynorbornene derivatives or grafted copolymer materials. The polynorbornene derivatives and grafted copolymer materials not only exhibit excellent functional properties but also enhanced physical and chemical properties after modification. The polynorbornene derivatives and grafted copolymer materials disclosed in the present invention exhibit excellent heat resistance, transparency and water resistance. The present invention also deals with a process for producing such derivatives and materials having controllable molecular weight with narrow molecular weight distribution.Type: GrantFiled: March 22, 2007Date of Patent: May 6, 2008Assignee: National Taiwan University of Science & TechnologyInventors: Der-Jang Liaw, Ching-Cheng Huang, Jing-Yang Ju, Jiun-Tyng Liaw
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Publication number: 20080099928Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: October 31, 2007Publication date: May 1, 2008Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Publication number: 20080083985Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.Type: ApplicationFiled: October 31, 2007Publication date: April 10, 2008Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7355288Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: GrantFiled: May 2, 2005Date of Patent: April 8, 2008Assignee: Megica CorporationInventors: Jin Yuan Lee, Ming Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Patent number: 7345365Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.Type: GrantFiled: December 3, 2003Date of Patent: March 18, 2008Assignee: MEGICA CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang