Patents by Inventor Ching-Chia Lin

Ching-Chia Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240166711
    Abstract: The present application provides a method for promoting the sternness and/or transdifferentiation of acinar cells, comprising the following steps: providing an acinar cell, transfecting a plasmid into the acinar cell, and culturing the transfected acinar cell, wherein the plasmid contains a genetic material for overexpression of N-acetylglucosaminyltransferase V (GnT-V).
    Type: Application
    Filed: November 18, 2022
    Publication date: May 23, 2024
    Inventors: Pei-Jen Lou, Tai-Horng Young, Ching-Chia Cheng, Mei-Chun Lin, Hisn-Lin Chen
  • Patent number: 11985324
    Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Patent number: 6630408
    Abstract: A new method is provided for the creation of an attenuated phase shifting mask. A transparent mask substrate is provided, a layer of attenuating phase shifting material is deposited on the surface of said transparent mask substrate, a layer of opaque material is deposited on the surface of said layer of attenuating phase shifting material. A layer of photoresist is deposited over the surface of the layer of opaque material. The photoresist is exposed by E-beam, creating a mask pattern and a guard ring pattern in the photoresist. The (E-beam) exposed photoresist is removed, the pattern created in the layer of photoresist is used to etch a mask pattern in the layer of opaque material and the layer of attenuating phase shifting material. The remaining photoresist is exposed to UV radiation in the region of the mask pattern and partially in the region of the guard ring.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: October 7, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: San-De Tzu, Ching-Chia Lin
  • Patent number: 6007324
    Abstract: A method of forming a rim type attenuating phase shifting mask which requires only one resist layer and developing the resist using a single developing solution. A transparent mask substrate has a layer of attenuating phase shifting material, a layer of opaque material, and a layer of resist material formed thereon. The layer of resist is exposed to a first pattern using a first exposure dose and a second pattern using a smaller second exposure dose. The resist is developed for a first time forming the first pattern in the entire layer of resist and the second pattern in the top portion of the layer of resist. The first pattern is then etched in the layer of opaque material using the first pattern in the layer of resist as a mask. In one embodiment the first pattern is then etched in the layer of attenuating phase shifting material, the resist is partially etched using an O.sub.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: December 28, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: San-De Tzu, Shy-Jay Lin, Ching-Chia Lin
  • Patent number: 5888678
    Abstract: A mask and a method of forming a mask having a binary mask pattern in a first region of a transparent mask substrate and a rim type attenuating phase shifting mask pattern in a second region of the same transparent mask substrate. The rim type attenuating phase shifting mask pattern is used to form small contact holes and the binary mask pattern is used to form larger contact holes in an integrated circuit wafer. The use of the rim type attenuating phase shifting mask pattern and the binary mask pattern avoids the problems due to side lobe effect for cases where different size contact holes are required on the same layer in an integrated circuit wafer. The formation of the rim type attenuating phase shifting mask pattern and the binary mask pattern on the same transparent mask substrate increases throughput and decreases cost in the fabrication of integrated circuit wafers.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: March 30, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: San-De Tzu, Chia-Hui Lin, Wen-Hong Huang, Ching-Chia Lin