Abstract: An integrated controlling chip includes a signal processing unit, a resistance unit and an electrostatic discharge protection circuit. The signal processing unit includes an input port. The resistance unit includes a first node coupled to a signal pin of the integrated controlling chip, and includes a second node coupled to the input port of the signal processing unit. The electrostatic discharge protection circuit includes a node coupled between the first node of the resistance unit and the signal pin of the integrated controlling chip.

Abstract: A switching signal generator of an active matrix display is disclosed. The switching signal generator includes at least one delay device connected to the switches of the active matrix display. The delay device consists of many delay units connected in series for receiving a source switching signal and correspondingly generating a plurality of target switching signals controlling the switches. There is a constant phase shift between any two successive target switching signals so that the switches are switched on one by one at regular intervals.

Abstract: A switching signal generator of an active matrix display is disclosed. The switching signal generator includes at least one delay device connected to the switches of the active matrix display. The delay device consists of many delay units connected in series for receiving a source switching signal and correspondingly generating a plurality of target switching signals controlling the switches. There is a constant phase shift between any two successive target switching signals so that the switches are switched on one by one at regular intervals.

Abstract: A device for driving a thin film transistor array of a liquid crystal display is provided. The device includes an input line, a plurality of latch units, and a plurality of digital-to-analog converters. The input line is used for receiving therefrom a plurality of digital image signals. The plurality of latch units are in communication with the input line for latching the digital image signals. The plurality of digital-to-analog converters are in communication with and disposed between the latch units and the data lines, for receiving more than one of the latched digital image signals, converting the latched digital image signals into analog image signals, and outputting the analog image signals to display cells in the same driven scan line via corresponding data lines synchronously. A method for driving a thin film transistor array of a liquid crystal display is also provided.

Abstract: A current source apparatus with bias switches, applied in digital-to-analog converters, is disclosed. The current compliance and settling time performances can be promoted via improving the structure of the bias circuit and making the MOS transistors operate in the saturation region, without increasing the dimensions of the MOS transistors.

Abstract: An address decoder having non-overlapping word line enable is disclosed having a dynamic logic gate-based decoding section. The decoder includes a deadtime signal generator that produces a pulse at the rising edge of every input clock cycle. The decoder further includes a transmission gate responsive to the deadtime signal for selectively passing the decoder section output signal to a latch. The decoder further includes a NOR logic having an output for coupling to a memory word line which is gated by the deadtime signal to disable the output while the transmission gate passes the decoder output to the latch. When the deadtime pulse transitions to a low state, the latch captures the decoder output signal and enables the output of the NOR gate.