Abstract: The present disclosure provides a method of manufacturing an image sensor device. The method comprises forming a first semiconductor chip including a matrix of image sensing cells and bonding a second semiconductor chip with the first semiconductor chip. A plurality of conductive vias are formed in the second semiconductor chip, where each of the plurality of conductive vias includes a first end substantially coplanar with a first surface of the first semiconductor chip and a second end in contact with a conductive trace in the second semiconductor chip. A first dielectric layer is formed over the plurality of conductive vias and a first conductive material is formed over the first dielectric layer. The first conductive material is etched to form a plurality of conductors coupled to ground and the plurality of conductors are electrically isolated from one another.

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured to receive light in a first direction from a light source. An interconnect structure is disposed over the first substrate, and includes a plurality of metal layers and insulating layers that are over stacked over one another in alternating fashion. One of the plurality of metal layers is closest to the light source and another of the plurality of metal layers is furthest from the light source. A bond pad recess extends into the interconnect structure from an opening in a surface of the 3DIC which is nearest the light source and terminates at a bond pad. The bond pad is spaced apart from the surface of the 3DIC and is in direct contact with the one of the plurality of metal layers that is furthest from the light source.

Abstract: Some embodiments of the present disclosure relate to an integrated chip having a via support structure underlying a bond pad. The integrated chip has an image sensing element arranged within a substrate. A bond pad region extends through the substrate, at a location laterally offset from the image sensing element, to a first metal interconnect wire arranged within a dielectric structure along a front-side of the substrate. A bond pad is arranged within the bond pad region and contacts the first metal interconnect wire. A via support structure is arranged within the dielectric structure and has one or more vias that are separated from the bond pad by the first metal interconnect wire. One or more additional vias are arranged within the dielectric structure at a location laterally offset from the bond pad region. The one or more vias have larger sizes than the one or more additional vias.

Abstract: The present disclosure, in some embodiments, relates to a CMOS image sensor. The CMOS image sensor has an image sensing element disposed within a substrate. A plurality of isolation structures are arranged along a back-side of the substrate and are separated from opposing sides of the image sensing element by non-zero distances. A doped region is laterally arranged between the plurality of isolation structures. The doped region is also vertically arranged between the image sensing element and the back-side of the substrate. The doped region physically contacts the image sensing element.

Abstract: Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler grid portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler grid portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.

Abstract: The present disclosure relates to a stacked SPAD image sensor with a CMOS Chip and an imaging chip bonded together, to improve the fill factor of the SPAD image sensor, and an associated method of formation. In some embodiments, the imaging chip has a plurality of SPAD cells disposed within a second substrate. The CMOS Chip has a first interconnect structure disposed over a first substrate. The imaging chip has a second interconnect structure disposed between the second substrate and the first interconnect structure. The CMOS Chip and the imaging chip are bonded together through along an interface disposed between the first interconnect structure and the second interconnect structure.

Abstract: The image sensing device includes a semiconductor substrate, an interconnection layer, a radiation-sensing region and an isolation structure. The semiconductor substrate has a front surface and a back surface. The interconnection layer is disposed over the front surface of the semiconductor substrate. The radiation-sensing region is disposed in the semiconductor substrate. The isolation structure is disposed on the back surface of the semiconductor substrate. The isolation structure includes a trench and an etch stop layer. The trench extends from the back surface of the semiconductor substrate. The etch stop layer is disposed along the trench. An etch selectivity of a silicon oxide film to the etch stop layer is greater than a predetermined value.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface opposing the first surface, and sidewalls defining a recess that passes through the semiconductor substrate. A first interconnect layer is within a first dielectric structure disposed along the second surface, and a bonding pad is in the recess and extends to the first interconnect layer. A dielectric filling layer is also within the recess. The dielectric filling layer has an opening over a portion of the bonding pad and a curved upper surface over the bonding pad. A nickel layer is over the bonding pad and in the opening.

Abstract: Embodiments of the present disclosure include an image sensor device and methods of forming the same. An embodiment is an image sensor device including a first plurality of pickup regions in a photosensor array area of a substrate, each of first plurality of pickup regions having a first width and a first length, a second plurality of pickup regions in a periphery area of the substrate, the periphery area along at least one side of the photosensor array area, each of second plurality of pickup regions having a second width and a second length.

Abstract: An image sensor structure and a method for forming the same are provided. The image sensor structure includes a first substrate including a first radiation sensing region and a first interconnect structure formed over a front side of the first substrate. The image sensor structure further includes a second substrate including a second radiation sensing region and a second interconnect structure formed over a front side of the second substrate. In addition, the first interconnect structure is bonded with the second interconnect structure.

Abstract: A device includes a semiconductor substrate, a plurality of micro-lenses disposed on the substrate, each micro-lens being configured to direct light radiation to a layer beneath the plurality of micro-lenses. The device further includes a transparent layer positioned between the plurality of micro-lenses and the substrate, the transparent layer comprising a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses, wherein the structure and the transparent material are coplanar at respective top surfaces and bottom surfaces thereof.

Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.

Abstract: A semiconductor device includes a substrate, light sensing devices, at least one infrared radiation sensing device, a transparent insulating layer, an infrared radiation cut layer, a color filter layer and an infrared radiation color filter layer. The light sensing devices and the at least one infrared radiation sensing device are disposed in the substrate and are adjacent to each other. The transparent insulating layer is disposed on the substrate overlying the light sensing devices and the at least one infrared radiation sensing device. The infrared radiation cut layer is disposed on the transparent insulating layer overlying the light sensing devices for filtering out infrared radiation and/or near infrared radiation. The color filter layer is disposed on the infrared radiation cut layer. The infrared radiation color filter layer is disposed on the transparent insulating layer overlying the at least one infrared radiation sensing device.

Abstract: Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler grid portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler grid portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.

Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess. The second surface is opposite to the first surface. The recess passes through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer over the second surface. The semiconductor device structure includes a first bonding pad in the recess and extending to the first wiring layer so as to be electrically connected to the first wiring layer. The semiconductor device structure includes a nickel layer over the first bonding pad. The semiconductor device structure includes a gold layer over the nickel layer.

Abstract: In some embodiments, the present disclosure relates to a method of forming a back-side image (BSI) sensor. The method may be performed by forming an image sensing element within a substrate and forming a pixel-level memory node at a position within the substrate that is laterally offset from the image sensing element. A back-side of the substrate is etched to form one or more trenches that are laterally separated from the image sensing element by the substrate and that vertically overlie the pixel-level memory node. A reflective material is formed within the one or more trenches.

Abstract: A backside illuminated (BSI) image sensor for biased backside deep trench isolation (BDTI) and/or biased backside shielding is provided. A photodetector is arranged in a semiconductor substrate, laterally adjacent to a peripheral opening in the semiconductor substrate. An interconnect structure is arranged under the semiconductor substrate. A pad structure is arranged in the peripheral opening, and protrudes through a lower surface of the peripheral opening to the interconnect structure. A conductive layer is electrically coupled to the pad structure, and extends laterally towards the photodetector from over the pad structure. A method for manufacturing the BSI image sensor is also provided.

Abstract: Embodiments of the present disclosure include an image sensor device and methods of forming the same. An embodiment is an image sensor device including a first plurality of pickup regions in a photosensor array area of a substrate, each of first plurality of pickup regions having a first width and a first length, a second plurality of pickup regions in a periphery area of the substrate, the periphery area along at least one side of the photosensor array area, each of second plurality of pickup regions having a second width and a second length.

Abstract: In some embodiments, the present disclosure relates to a back-side image (BSI) sensor having a global shutter pixel with a reflective material that prevents contamination of a pixel-level memory node. In some embodiments, the BSI image sensor has an image sensing element arranged within a semiconductor substrate and a pixel-level memory node arranged within the semiconductor substrate at a location laterally offset from the image sensing element. A reflective material is also arranged within the semiconductor substrate at a location between the pixel-level memory node and a back-side of the semiconductor substrate. The reflective material has an aperture that overlies the image sensing element. The reflective material allows incident radiation to reach the image sensing element while preventing the incident radiation from reaching the pixel-level memory node, thereby preventing contamination of the pixel-level memory node.