Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A package structure, including a circuit board, multiple circuit structure layers, at least one bridge structure, and at least one supporting structure, is provided. The circuit structure layer is disposed on the circuit board. The bridge structure is connected between the two adjacent circuit structure layers. The supporting structure is located between the two adjacent circuit structure layers, and the supporting structure has a first end and a second end opposite to each other and respectively connecting the bridge structure and the circuit board.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: The present disclosure discloses a multi-core processing circuit having power-stabilizing test mechanism that includes a plurality of core-processing circuits arranged in an order and a self-test scheduling circuit. Each of the core-processing circuits includes a memory built-in self-test circuit. The self-test scheduling circuit receives a main activation signal to activate the memory built-in self-test circuit of one of the core-processing circuits every delay time in the order based on signal handshake to perform self-test, wherein one of the activated core-processing circuits has a largest average power draining amount in a predetermined range within the delay time.

Abstract: A motor module and a water-cooling pump having motor module are provided. The motor module has a combined first shell and second shell, a driving shaft mounted on the first shell and second shell, the stator assembly is mounted in the first shell, and the rotor assembly is mounted on the driving shaft. An opening of the first shell forms a first mounting portion, which can be mounted on or detached from a second mounting portion of the second shell via easy means. The modularized motor module can be mounted into a water machine via an opening of a shell and then a motor cover is mounted on the opening of the shell, and a drawing mechanism and pressured housing can be mounted at another end, so the assembling process is easy.

Abstract: An antenna switching system is provided. The system includes a radio frequency (RF) circuit for transmitting and receiving signals, a first antenna, a second antenna, a first switch, a first switch assembly, a second switch assembly, and a power divider. The first switch electrically connected to the RF circuit. The first switch assembly electrically connected between the first switch and the first antenna. The second switch assembly electrically connected between the first switch and the second antenna. The power divider electrically connected between the first switch and the first switch assembly and between the first switch and the second switch assembly. When the first switch is switched to the power divider, the signals are transmitted by the first antenna and the second antenna.

Abstract: An antenna switching system is provided. The system includes a radio frequency (RF) circuit for transmitting and receiving signals, a first antenna, a second antenna, a first switch, a first switch assembly, a second switch assembly, and a power divider. The first switch electrically connected to the RF circuit. The first switch assembly electrically connected between the first switch and the first antenna. The second switch assembly electrically connected between the first switch and the second antenna. The power divider electrically connected between the first switch and the first switch assembly and between the first switch and the second switch assembly. When the first switch is switched to the power divider, the signals are transmitted by the first antenna and the second antenna.

Abstract: An antenna switching system is provided. The system includes a radio frequency (RF) circuit for transceiving signals, N antennas, a master switch, N switches, and N power dividers. The signals may be transmitted by one of the N antennas, or the signals are transmitted by the antennas of the N antennas.

Abstract: A wireless communication device and a filter are provided. The filter has an input end and an output end and includes a first energy storage element, a first series resonant circuit, a second series resonant circuit, a first parallel resonant circuit and a second parallel resonant circuit. The first and the second series resonant circuits respectively have a first capacitor and a first inductor connected in series. The first and the second parallel resonant circuits respectively have a second capacitor and a second inductor connected in parallel. The first series resonant circuit and the first parallel resonant circuit are electrically connected in cascade between a first end of the first energy storage element and a ground, and the second series resonant circuit and the second parallel resonant circuit are electrically connected in cascade between a second end of the first energy storage element and the ground.

Abstract: A dual-mode telecommunication device and its driving method are disclosed. The dual-mode telecommunication device electrically connects with a voice input/output communication unit for transmitting/receiving an analog voice signal. In addition, the dual-mode telecommunication device comprises a processor and a switch, wherein the processor is used for detecting/transforming the signal type and generating a control signal based on a detection result. The switch is used for assisting the voice input/output communication unit performing an Internet telecommunication mode or a PSTN (Public Switched Telephone Network) telecommunication mode, alternatively based on the control signal. The driving method is used for determining whether assisting the voice input/output communication unit to electrically connect with the Internet or not by the switch based on detecting a signal which contains an IP, a status result and a dial-tone result of the voice input/output communication unit.

Abstract: A method of processing a frame including a plurality of macro-blocks is provided. Each of the macro-blocks respectively includes M pixels. A local buffer is previously provided. The capacity of the local buffer is equal to the size of N pixels. M and N are both positive integers. N is smaller than or equal to M. A target area is first selected from the micro-blocks, and then N pixels within the target area are stored in the local buffer. Afterward, the method performs a deblock filtering procedure on the N pixels stored in the local buffer.

Abstract: An etching reaction device (3) includes an etching reaction chamber (30), and a number of protrusions (301) arranged on the bottom of the etching reaction chamber. Thus it can economize the etching time and quickly complement the concentration of the etching liquid near to a wafer (7). The protrusions can reduce the capability of the etching reaction chamber, thus it can economize the etching liquid.