Abstract: A resonant amplifier is provided. A resonant inductor is connected in series between a source (emitter) of a common gate (base) transistor and an input point (i.e. output point of previous stage), and a resonant capacitor is connected between the input point and a ground or a voltage source connected to a loading end, such that a lossy resonant cavity is formed for carrying out resonance to amplify the signal. Then, the amplified signal is drawn out by the common gate (base) architecture. Therefore, the gain of the resonant amplifier can be boosted at desired frequency.

Abstract: A variable-gain wide-dynamic-range amplifier including an amplifier module, a control unit, and an output current regulating circuit is provided. The amplifier module amplifies an input signal. The amplifier module includes several amplifier units coupled to each other in parallel. The gains of the amplifier units are different. The control unit enables at least one of the amplifier units according to a gain control signal. The at least one of the amplifier units which is enabled is for outputting a current signal in response to the input signal. The output regulating circuit is for receiving the current signal and outputting an output signal accordingly by regulating the magnitude of the current signal under the control of the control unit. Each of the amplifier units is coupled to the output current regulating circuit in series. The control unit is for controlling the output current regulating circuit according to the gain control signal.

Abstract: Disclosed is an apparatus for multiple-divisor prescaler, which includes an odd/even core divider, a divisor control logic unit, an odd number inserted mechanism, and an n-order divided-by-2 divider with changeable trigger edges. This invention uses a clock toggle mechanism to vary the trigger edges of each divided-by-2 divider in the n-order divider, and associates the odd/even core divider to realize the multiple-divisor prescaler apparatus. Thereby, it achieves the purpose of being divided by 30/31. In addition, it increases the divisor range up to 2n?1+2 and 2n+1 through the use of the clock toggle mechanism.

Abstract: Disclosed is an apparatus for multiple-divisor prescaler, which includes an odd/even core divider, a divisor control logic unit, an odd number inserted mechanism, and an n-order divided-by-2 divider with changeable trigger edges. This invention uses a clock toggle mechanism to vary the trigger edges of each divided-by-2 divider in the n-order divider, and associates the odd/even core divider to realize the multiple-divisor prescaler apparatus. Thereby, it achieves the purpose of being divided by 30/31. In addition, it increases the divisor range up to 2n?1+2 and 2n+1 through the use of the clock toggle mechanism.

Abstract: A resonant amplifier is provided. A resonant inductor is connected in series between a source (emitter) of a common gate (base) transistor and an input point (i.e. output point of previous stage), and a resonant capacitor is connected between the input point and a ground or a voltage source connected to a loading end, such that a lossy resonant cavity is formed for carrying out resonance to amplify the signal. Then, the amplified signal is drawn out by the common gate (base) architecture. Therefore, the gain of the resonant amplifier can be boosted at desired frequency.

Abstract: A FM demodulator using a single input signal has two I-Q splitters with constant group delay apparatuses. During operation, t two I-Q splitters with constant group delay apparatuses may receive the input modulated signal to generate not only one pair of modulated and respectively delay &tgr;1 and &tgr;2 in phase signals but also another pair of modulated and respective delay &tgr;1 and &tgr;2 quadrature signals. These signals are used to demodulate the final demodulated signal.

Abstract: A FM demodulator using a single input signal has two I-Q splitters with constant group delay apparatuses. During operation, t two I-Q splitters with constant group delay apparatuses may receive the input modulated signal to generate not only one pair of modulated and respectively delay &tgr;1 and &tgr;2 in phase signals but also another pair of modulated and respective delay &tgr;1 and &tgr;2 quadrature signals. These signals are used to demodulate the final demodulated signal.