Abstract: A wheel rim includes a rim body including a central member and a peripheral well with a tire secured thereon wherein the central member includes an outboard tire bead seat is formed between an outer annular flange of the peripheral well and an inner annular ridge thereof, an inboard tire bead seat is formed between an inner annular flange of the peripheral well and an outer annular ridge thereof, an outboard tire bead of the tire is mounted on the outboard tire bead seat, an inboard tire bead of the tire is mounted on the inboard tire bead seat, and a diameter of the outer annular flange is less than that of the inn annular flange so that a replacement of the tire can be made by removing it through a peripheral opening; and a ring releasably secured to a peripheral edge of the rim body.

Abstract: The invention relates to a theft-prevention system for a mobile phone, primarily comprising a detection control system and a mobile phone, wherein the detection control system includes a microwave emitter, detection unit, and alarm tone, and a microwave reception unit is fit within the mobile phone, with said microwave reception unit being integrated into the mobile phone system; as a result, when the detection control system senses that someone is approaching or breaking in, it will emit a microwave signal to the microwave reception unit, while at the same time emitting an alarm tone, as well as activating the speaker of the mobile phone to notify the user indicates that someone has come within the set range, allowing the owner of the mobile phone to immediately act in response. The invention thus provides a more user-friendly, mobile phone-integrated theft-prevention system.

Abstract: This invention is a type of mobile telephone with anti-theft functionality, primarily a mobile telephone with a detection beam emission system inside. The detection beam emission system has a sensor module (e.g. an infrared or human detection device) and a drive unit, and once the anti-theft function is activated, when a person approaches within a certain distance of the place where the mobile phone is placed, it will activate the telephone to emit a sound to attract attention to the person approaching, thereby achieving better anti-theft functionality in a mobile phone in order to protect personal property.

Abstract: A combined lens rim injection molded with soft raw material includes an upper rim and a lower rim combined together. The upper rim and the lower rim are designed to be so simple that the lens rim can easily be released from the mold through the opening. By so designing, in case of opening the mold, the upper rim and the lower rim can be automatically released from the mold by means of ejector pins or mechanical arms, able to save man power for removing the lens rim out of the mold, simplify a solid lens-rim mold and reduce cost of opening mold as well as time required for injection molding.

Abstract: A safety helmet with a slidable lens includes a helmet body, and a lens and two sliding rails. The slidable rails are fixed spaced apart properly on a front portion of the helmet body, and the lens has two fitting pins spaced apart on the lens to correspond to and slide up and down along the slidable rails. So the lens can be pulled to slide up and down relative to the helmet body for used or tucked away to closely rest on the helmet body, not to resist wind in case of tucked away.

Abstract: An eyesight correction lens includes a seeing region and a combining surface that is made of a material able to be sucked on a smooth lens. The eyesight correction lens can be positioned on the lens of eyeglasses so that a person with poor eyesight can not only protect his eyes but also see things clearly through the seeing region of the eyesight correction lenses. Since the seeing region of the eyesight correction lens does not contact with the lens of the eyeglasses, no air bubbles will be produced therebetween and hence things can be seen clearly through them. The eyesight correction lens of this invention can be combined on the lens of different eyeglasses for use and also can be removed from the eyeglasses when a user need not see things at a short distance, convenient in use.

Abstract: A data transmission circuit has an internal circuit for providing data, a register electrically connected to the internal circuit for temporarily storing the data transmitted from the input internal circuit, and a control circuit for controlling operations of the data transmission circuit. If data inputted to the register is specific data, the internal circuit will repeatedly output the specific data to the register so as to prolong transmission time of the specific data.

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract: An enhanced Printed Circuit Board (PCB) and stacked substrate structure. In one embodiment, each middle layer is coupled between two ground layers except for the top signal layer and the bottom solder layer. In another embodiment, the top signal layer and the bottom solder layer are respectively coupled between two ground layers, so all signal layers are implemented in the stacked substrate structure and any internal signal layer is coupled between two ground layers. Thus, all signals can refer to adjacent ground layers and achieve better signal quality. Also, each capacitance structure formed by a signal layer and a ground layer increases the operating speed of the entire circuit.

Abstract: A control circuit, a chipset and a method capable of saving the terminal resistors on a motherboard. Through the determination of connection of a pull-up enable line to a first voltage source Vdd via a resistor, an equivalent resistance is set between the source terminal and the drain terminal of a field effect transistor. The equivalent resistance is almost identical to the terminal resistor and hence can replace the resistor on the motherboard. When the pull-up enable line is connected to the first voltage source Vdd via a resistor, an equivalent resistance of about 45-60&OHgr; is established between the source and drain terminal of the field effect transistor. The equivalent resistance is connected in parallel with an input/output pad and a second voltage source Vtt to replace the original externally connected terminal resistor rt2 at the other end of the bus.

Abstract: The present invention provides an integrated circuit with high-frequency signals immune from noises. The integrated circuit has a chip having a first pad and a plurality of second pads, wherein an AC signal and DC signals are transmitted through the first pad and the second pads respectively, a substrate having a first finger and a plurality of second fingers, a first conducting line connected between the first pad and finger respectively of the chip and substrate, and a plurality of second conducting lines connected between the second pads and fingers respectively of the chip and substrate, and surrounding the first conducting line.

Abstract: A dual processor adapter card with a plurality of electrical pins for inserting into a processor slot on a mainboard by which the adapter card is electrically coupled to the mainboard. There is a first and a second processor socket on the adapter card for carrying a first and a second processor respectively. The first and the second processor socket each has a plurality of corresponding pins, a portion of the pins of the first and the second processor socket corresponds to a portion of the electrical pins. Corresponding pins are coupled together. Furthermore, each of the pins that act as a terminal lead in the first and the second processor socket is connected to a pull-up resistor, and the pull-up resistor is connected to a terminal voltage. In addition, a zero-delay buffer for synchronizing clock pulse signals and a voltage regulator for regulating a power voltage into a suitable working voltage are mounted on the adapter card and coupled to the first and the second processor socket respectively.

Abstract: A system can produce a suitable voltage for powering the memory modules plugged into the memory module slots of a motherboard. A power-good signal is issued when the motherboard is powered up. A power safety device on the motherboard then issues a 2.5V to the memory module slot. If DDR DRAM type of memory modules are not detected after a while, the power safety device will turn off the 2,5V supply and provide a 3.3V, which is suitable for SDRAM type memory modules.This invention avoids sending a 3.3V to DDR DRAM modules, thereby burning the memory chip. The presence of DDR DRAM modules can be detected by a general-purpose purpose input/output port through accessing the recorded data in the EEPROM of the memory module. Alternatively, memory module type can be determined by sending out a low-current pulse signal to the memory module slot. Hence, a suitable voltage source is automatically provided to power the memory modules in the slots.

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract: A data transmission circuit has an internal circuit for providing data, a register electrically connected to the internal circuit for temporarily storing the data transmitted from the input circuit, and a control circuit for controlling operations of the data transmission circuit.

Abstract: A trace layout of a printed circuit board (PCB) is provided with a north bridge, at least a peripheral component interconnect (PCI) slot, and an accelerate graphics port (AGP) slot. The PCB includes at least a first trace layer and a second trace layer under the first trace layer. The AGP slot is mounted between the north bridge and the PCI slot. The PCB further includes a number of first traces, and a number of second traces. The first traces are used for connecting the north bridge to the PCI slot while the second traces are used to connect the north bridge to the AGP slot. Some of the first traces are on the second trace layer under the AGP slot, while the other of the first traces are on the first trace layer or the second trace layer and trace aside the AGP slot. Most of the second traces are on the first trace layer and the other of the second traces are on the second trace layer.

Abstract: A control circuit, a chipset and a method capable of saving the terminal resistors on a motherboard. Through the determination of connection of a pull-up enable line to a first voltage source Vdd via a resistor, an equivalent resistance is set between the source terminal and the drain terminal of a field effect transistor. The equivalent resistance is almost identical to the terminal resistor and hence can replace the resistor on the motherboard. When the pull-up enable line is connected to the first voltage source Vdd via a resistor, an equivalent resistance of about 45-60 &OHgr; is established between the source and drain terminal of the field effect transistor. The equivalent resistance is connected in parallel with an input/output pad and a second voltage source Vtt to replace the original externally connected terminal resistor rt2 at the other end of the bus.

Abstract: A system can produce a suitable voltage for powering the memory modules plugged into the memory module slots of a motherboard. A power-good signal is issued when the motherboard is powered up. A power safety device on the motherboard then issues a 2.5V to the memory module slot. If DDR DRAM type of memory modules are not detected after a while, the power safety device will turn off the 2.5V supply and provide a 3.3V, which is suitable for SDRAM type memory modules. This invention avoids sending a 3.3V to DDR DRAM modules, thereby burning the memory chip. The presence of DDR DRAM modules can be detected by a general-purpose input/output port through accessing the recorded data in the EEPROM of the memory module. Alternatively, memory module type can be determined by sending out a low-current pulse signal to the memory module slot. Hence, a suitable voltage source is automatically provided to power the memory modules in the slots.

Abstract: An input/output (I/O) buffer with reduced ring-back effect is provided. This I/O buffer is designed for a data transmission bus, such as a GTL+bus, for the transmission of a high-frequency and low-swing data signal. This I/O buffer is designed for the purpose of reducing the undesirable ring-back effect in the I/O buffer. The I/O buffer is characterized by the provision of a variable-resistance device that is connected between the system voltage and the input end of the I/O buffer. The system voltage is set to be equal in magnitude to the high-voltage logic state of the data signal received by the I/O buffer from the data transmission bus. When the input data signal is higher in magnitude than a preset reference voltage, i.e., at the high-voltage logic state, the variable-resistance device is switched to a low resistance value; on the other hand, when the data signal is lower in magnitude than the reference voltage, the variable-resistance device is switched to a near-infinity resistance value.

Abstract: An impedance adjusting apparatus of a controlling chip on a computer mainboard. When a computer is turned on, BIOS automatically detects the actual usage of the memory sockets, and then sends corresponding control signals to adjust the impedance of the impedance adjusting apparatus for a better impedance matching between the controlling chip and the memory sockets. The signal reflection is dramatically reduced and the operation bandwidth is widened.