Patents by Inventor Ching Ho

Ching Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240358826
    Abstract: The present invention relates, in part, to chimeric proteins, chimeric protein complexes, vaccine compositions, and adjuvants that include IL-1? or pro-IL-1? and their use as therapeutic agents or vaccines. The present invention further relates to methods of treatment of various diseases, such as infectious diseases and cancer and methods of vaccination.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 31, 2024
    Inventors: Nikolai KLEY, Erik DEPLA, Joris WAUMAN, Enkeleda NAKUCI, Yen-Ching HO, Alexander Lee KLEY
  • Publication number: 20240363545
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.
    Type: Application
    Filed: July 14, 2023
    Publication date: October 31, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu LEE, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Po-Yuan SU
  • Patent number: 12125848
    Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ching Wang, Chun-Chung Su, Chung-Wei Wu, Jon-Hsu Ho, Kuan-Lun Cheng, Wen-Hsing Hsieh, Wen-Yuan Chen, Zhi-Qiang Wu
  • Patent number: 12125828
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: October 22, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20240322651
    Abstract: A cooling motor includes a motor device having a motor casing, a motor assembly arranged in the motor casing, and a centrifugal fan, and a cooling device having first and second cooling components. The first cooling component includes a first cold plate jacket and a first heat circulation pipeline. The first cold plate jacket is sleeved on the motor assembly and thermally connected to a stator, and the first cold plate jacket includes first cold plates. The first thermal circulation pipeline filled with a first working fluid passes through the first cold plate jacket. The second cooling component includes a second cold plate jacket and a second heat circulation pipeline. The second cold plate jacket, sleeving the first cold plate jacket in an insulation manner, includes second cold plates and cooling fins. The second thermal circulation pipeline filled with a second working fluid passes through the second cold plate jacket.
    Type: Application
    Filed: June 9, 2023
    Publication date: September 26, 2024
    Inventors: Kwun-Yao HO, Szu-Hsien LIU, Yao-Ching HUANG, Chia-Wei LIU
  • Publication number: 20240319262
    Abstract: An integrated circuit includes first and second pads, a buffer circuit coupled to the first pad, a first pass gate circuit coupled to the first pad and to the buffer circuit, a second pass gate circuit coupled to the second pad, and a test bus coupled to the first pass gate circuit and the second pass gate circuit. The first pass gate circuit and the second pass gate circuit are configurable to couple the second pad to the buffer circuit through the test bus during a test of the buffer circuit that is performed using the second pad.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Altera Corporation
    Inventors: Pai Ho Bong, Sean Woei Voon, Ching Sia Lim, Wee Sun Voon
  • Patent number: 12101881
    Abstract: A circuit board assembly is provided and includes a first circuit board, a second circuit board and a first connecting module. The first connecting module includes a first connecting wire, a first connector and a second connector. The first circuit board includes a first processor, and the second circuit board includes a second processor. One end of the first connector is connected to one end of the first connecting wire, and the other end of the first connector is connected to the first circuit board. One end of the second connector is connected to the other end of the first connecting wire, and the other end of the second connector is connected to the second circuit board. The first connector is adjacent to the first processor, and the second connector is adjacent to the second processor.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: September 24, 2024
    Assignee: Unimicron Technology Corporation
    Inventors: Ching-Ho Hsieh, Ming-Hsing Wu, Kuei-Sheng Wu
  • Publication number: 20240302727
    Abstract: A projection device including a casing, an illumination system, a light valve, a first casing member, a second casing member and a projection lens. A color wheel module of the illumination system includes a fixing base, an optical assembly, a first connecting assembly and a second connecting assembly. A driving assembly of the optical assembly is connected to a center of a disk of the optical assembly. On a reference plane perpendicular to the central axis, an orthogonal projection of the first connecting portion and an orthogonal projection of the second connecting portion are respectively located on two sides of the central axis, wherein the first connecting portion of the fixing base is connected to the first casing member through the first connecting assembly, and the second connecting portion is connected to the second casing member through the second connecting assembly.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 12, 2024
    Applicant: Coretronic Corporation
    Inventors: Wen-Ching Ho, Shi-Wen Lin
  • Publication number: 20240290701
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 29, 2024
    Inventors: Yi-Min FU, Chi-Ching HO, Cheng-Yu KANG, Yu-Po WANG
  • Patent number: 12068271
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Grant
    Filed: July 23, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
  • Publication number: 20240274519
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 15, 2024
    Inventors: Yi-Min FU, Chi-Ching HO, Cheng-Yu KANG, Yu-Po WANG
  • Publication number: 20240264389
    Abstract: An electronic package and the manufacturing method thereof are provided, in which a photonic element and an electronic element are embedded in an encapsulation layer, and the photonic element has an external contact area exposed from the encapsulation layer, such that signals of the electronic element can be directly transmitted to an optical fiber via the external contact area of the photonic element to achieve the purpose of photoelectric integration.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 8, 2024
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Che-Yu LEE, Po-Yuan SU
  • Publication number: 20240258407
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members vertically stacked above a substrate, a gate structure engaging the channel members, a gate sidewall spacer disposed on a sidewall of the gate structure, an epitaxial feature abutting end portions of the channel members, and inner spacers interposing the gate structure and the epitaxial feature. The end portion of at least one of the channel members includes a first dopant. A concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members. The concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.
    Type: Application
    Filed: April 1, 2024
    Publication date: August 1, 2024
    Inventors: Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 12051641
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: July 30, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Cheng-Yu Kang, Yu-Po Wang
  • Publication number: 20240239986
    Abstract: A copolyester is formed by copolymerizing a depolymerized polyester and succinic acid. The depolymerized polyester includes depolymerized polyethylene terephthalate (PET), and the depolymerized PET is formed by depolymerizing PET with ethylene glycol. The repeating unit of PET and the succinic acid have a molar ratio of 40:60 to 50:50. The repeating unit of PET and the ethylene glycol have a molar ratio of 100:100 to 100:500. The copolyester has a storage modulus of 1*104 Pa to 1*106 Pa at 80° C. The copolyester can be used in a hot melt adhesive.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Che-Tseng LIN, Meng-Hsin CHEN, Jen-Chun CHIU, Kai-Chuan KUO, Yu-Lin CHU, Po-Hsien HO, Ke-Hsuan LUO, Chih-Hsiang LIN, Hui-Ching HSU
  • Patent number: 12032165
    Abstract: A glasses type display device including a front end assembly and a pair of legs is provided. Each of the pair of legs includes a front segment, a rear segment, a torsion mechanism, and a rotation mechanism. The torsion mechanism is disposed between the front end assembly and the front segment. The rotation mechanism is disposed between the front segment and the rear segment.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: July 9, 2024
    Assignee: HTC Corporation
    Inventors: Tung-Hsin Yeh, Ching-Ho Li, Wei-Cheng Liu, Chun-Lung Chu
  • Publication number: 20240222965
    Abstract: A driving circuit includes a detection circuit, a control circuit, and a power device. The detection circuit is coupled between first and second power terminals. The detection circuit generates a detection voltage at a detection node based on a first voltage of the first power terminal and a second voltage of the second power terminal. The control circuit includes a transistor device with a back-to-back connection structure that is coupled between a bonding pad and a first node and controlled by the detection voltage to generate a driving voltage at the first node for controlling the power device. In response to an electrostatic discharge event occurring on the bonding pad, the transistor device is turned on according to the detection voltage, and the power device is triggered by the driving voltage to provide a discharge path between the bonding pad and the second power terminal.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Ching-Ho LI, Chun-Chih CHEN, Kai-Chieh HSU, Chien-Wei WANG, Chih-Hsuan LIN, Hwa-Chyi CHIOU, Gong-Kai LIN, Li-Fan CHEN
  • Publication number: 20240164474
    Abstract: A skate includes a skate boot and wheel assembly; an outer seat disposed on the skate boot and wheel assembly; an inner seat disposed in the outer seat; a tongue disposed on the inner seat; a cover disposed on the tongue; a first hole disposed in a toe portion of the outer seat; a second hole disposed in front of the first hole; a biasing member disposed in both the first and second holes; two projections having a through hole disposed on a front end of the cover; and a pivot disposed through the through holes and the biasing member to assemble the cover and the outer seat. Thus, the tongue is pivotal.
    Type: Application
    Filed: August 11, 2023
    Publication date: May 23, 2024
    Inventor: Ching-Ho Yeh
  • Patent number: 11991797
    Abstract: A LED power supply with bi-level dimming receives an input voltage to supply power to an LED lamp, and adjusts the brightness of the LED lamp according to whether an external detection switch is triggered to be turned on. The LED power supply includes a conversion circuit, a switch, and an oscillation circuit. The conversion circuit converts the input voltage into an output voltage, and provides the output voltage to supply power to the LED lamp so as to control the LED lamp to provide a first brightness. The oscillation circuit provides a dimming signal with a fixed frequency and a duty cycle to the switch when the external detection switch is turned on so as to turn on and turn off the switch. The switch correspondingly adjusts the output voltage according to the dimming signal to control the LED lamp to provide a second brightness.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: May 21, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ching-Ho Chou, Yung-Chuan Lu
  • Patent number: D1047989
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 22, 2024
    Assignee: EVOLUTIVE LABS CO., LTD.
    Inventors: Ching-Fu Wang, Jui-Chen Lu, Po-Wen Hsiao, Chia-Ho Lin