Patents by Inventor Ching-Hua Hsieh
Ching-Hua Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11764127Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.Type: GrantFiled: February 26, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
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Patent number: 11756872Abstract: A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.Type: GrantFiled: March 11, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
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Publication number: 20230282629Abstract: A semiconductor package includes a first integrated circuit and a first waveguide. The first integrated circuit includes an optical coupler. The first waveguide is optically coupled to the optical coupler. In some embodiments, the first waveguide protrudes beyond the optical coupler. In some embodiments, the first waveguide is partially overlapped with the optical coupler.Type: ApplicationFiled: May 10, 2023Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Ching-Hua Hsieh, Chih-Wei Lin, Yu-Hao Chen
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Publication number: 20230282555Abstract: A package structure includes a first package, a second package, a conductive spacer, and a flux portion. The first package includes a semiconductor die. The second package is stacked to the first package. The conductive spacer is disposed between and electrically couples the first package and the second package. The flux portion is disposed between and electrically couples the first package and the conductive spacer, where the flux portion includes a first portion and a second portion separating from the first portion by a gap, and the first portion and the second portion are symmetric about an extending direction of the gap. The gap is overlapped with the conductive spacer.Type: ApplicationFiled: March 2, 2022Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chiang Tsao, Chao-Wei Chiu, Jen-Jui Yu, Hsiu-Jen Lin, Ching-Hua Hsieh
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Publication number: 20230268316Abstract: A package structure includes a semiconductor device including a conductive feature, a joint layer, a pillar structure, an encapsulant and a RDL structure. The joint layer is disposed on the conductive feature. The pillar structure is disposed on and coupled to the semiconductor device through the joint layer. The encapsulant laterally encapsulates the semiconductor device and the pillar structure. The RDL structure is electrically connected to the semiconductor device.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh
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Patent number: 11731327Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.Type: GrantFiled: July 29, 2022Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Feng Weng, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Sheng-Hsiang Chiu, Yao-Tong Lai, Chia-Min Lin
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Publication number: 20230260961Abstract: A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Fung Chang, Sheng-Feng Weng, Ming-Yu Yen, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 11721659Abstract: A package structure is provided. The package structure includes a semiconductor die and a molding compound layer surrounding the semiconductor die. The package structure also includes a conductive bump over the molding compound layer and a first polymer-containing layer surrounding and in contact with the conductive bump. The package structure further includes a second polymer-containing layer disposed over the first polymer-containing layer. A bottom surface of the conductive bump is below a bottom surface of the second polymer-containing layer.Type: GrantFiled: June 28, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20230230849Abstract: A method includes forming an insulating layer over a package. The package has a plurality of locations where openings are subsequently formed. A first laser shot is performed, location by location, on each of the locations across the package. A first laser spot of the first laser shot overlaps with each of the locations. The first laser shot removes a first portion of the insulating layer below the first laser spot. Another laser shot is performed, location by location, on each of the locations across the package. Another laser spot of the another laser shot overlaps with each of the locations. The another laser shot removes another portion of the insulating layer below the another laser spot. Performing the another laser shot, location by location, on each of the locations across the package is repeated multiple times, until desired portions of the insulating layer are removed.Type: ApplicationFiled: May 4, 2022Publication date: July 20, 2023Inventors: Chia-Shen Cheng, Chia-Lun Chang, Hao-Jan Pei, Hsiu-Jen Lin, Ching-Hua Hsieh
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Patent number: 11705409Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.Type: GrantFiled: June 29, 2020Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
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Publication number: 20230215837Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The apparatus includes a first support configured to carry a first semiconductor substrate and a second semiconductor substrate bonded to each other, a gauging component embedded in the first support and comprising a fiducial pattern, and a first sensor disposed proximate to the gauging component, and configured to emit a light source towards the fiducial pattern of the gauging component.Type: ApplicationFiled: March 15, 2023Publication date: July 6, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Jui Huang, Ching-Hua Hsieh, Chien-Ling Hwang, Chia-Sheng Huang
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Patent number: 11688725Abstract: A semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a waveguide. The photonic integrated circuit includes an optical coupler. The electronic integrated circuit is disposed aside the photonic integrated circuit. The waveguide is optically coupled to the optical coupler, wherein the waveguide is disposed at an edge of the photonic integrated circuit and protrudes from the edge of the photonic integrated circuit.Type: GrantFiled: January 18, 2022Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Ching-Hua Hsieh, Chih-Wei Lin, Yu-Hao Chen
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Publication number: 20230197671Abstract: A system for reflowing a semiconductor workpiece including a stage, a first vacuum module and a second vacuum module, and an energy source is provided. The stage includes a base and a protrusion connected to the base, the stage is movable along a height direction of the stage relative to the semiconductor workpiece, the protrusion operably holds and heats the semiconductor workpiece, and the protrusion includes a first portion and a second portion surrounded by and spatially separated from the first portion. The first vacuum module and the second vacuum module respectively coupled to the first portion and the second portion of the protrusion, and the first vacuum module and the second vacuum module are operable to respectively apply a pressure to the first portion and the second portion. The energy source is disposed over the stage to heat the semiconductor workpiece held by the protrusion of the stage.Type: ApplicationFiled: February 22, 2023Publication date: June 22, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Shiuan Wong, Ching-Hua Hsieh, Hsiu-Jen Lin, Hao-Jan Pei, Hsuan-Ting Kuo, Wei-Yu Chen, Chia-Shen Cheng, Philip Yu-Shuan Chung
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Publication number: 20230187383Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.Type: ApplicationFiled: February 3, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Lin, Chun-Yen Lan, Tzu-Ting Chou, Tzu-Shiun Sheu, Chih-Wei Lin, Shih-Peng Tai, Wei-Cheng Wu, Ching-Hua Hsieh
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Publication number: 20230178536Abstract: A method includes forming a reconstructed wafer, which includes placing a plurality of device dies over a carrier, encapsulating the plurality of device dies in an encapsulant, and forming a redistribution structure over the plurality of device dies and the encapsulant. The redistribution structure includes a plurality of dielectric layers and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes performing a trimming process on the reconstructed wafer. The trimming process forms a round edge for the reconstructed wafer. A sawing process is performed on the reconstructed wafer, so that the reconstructed wafer includes straight edges.Type: ApplicationFiled: March 22, 2022Publication date: June 8, 2023Inventors: Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Cheng-Shiuan Wong, Hsiu-Jen Lin, Ching-Hua Hsieh
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Publication number: 20230168451Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.Type: ApplicationFiled: February 1, 2023Publication date: June 1, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hsuan-Ting Kuo, Chia-Shen Cheng, Chih-Chiang Tsao
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Patent number: 11664300Abstract: A device may include a first package and a second package where the first package has a warped shape. First connectors attached to a redistribution structure of the first package include a spacer embedded therein. Second connectors attached to the redistribution structure are fee from the spacer, the spacer of the first connectors keeping a minimum distance between the first package and the second package during attaching the first package to the second package.Type: GrantFiled: December 26, 2019Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chiang Tsao, Chao-Wei Chiu, Hsuan-Ting Kuo, Chia-Lun Chang, Cheng-Shiuan Wong, Hsiu-Jen Lin, Ching-Hua Hsieh
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Publication number: 20230154764Abstract: A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.Type: ApplicationFiled: March 21, 2022Publication date: May 18, 2023Inventors: Tzu-Sung Huang, Tsung-Hsien Chiang, Ming Hung Tseng, Hao-Yi Tsai, Yu-Hsiang Hu, Chih-Wei Lin, Lipu Kris Chuang, Wei Lun Tsai, Kai-Ming Chiang, Ching Yao Lin, Chao-Wei Li, Ching-Hua Hsieh
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Patent number: 11646293Abstract: A method for bonding semiconductor substrates includes placing a die on a substrate and performing a heating process on the die and the substrate to bond the respective first connectors with the respective second connectors. Respective first connectors of a plurality of first connectors on the die contact respective second connectors of a plurality of second connectors on the substrate. The heating process includes placing a mask between a laser generator and the substrate and performing a laser shot. The mask includes a masking layer and a transparent layer. Portions of the masking layer are opaque. The laser passes through a first gap in the masking layer and through the transparent layer to heat a first portion of a top side of the die opposite the substrate.Type: GrantFiled: July 22, 2020Date of Patent: May 9, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Shen Cheng, Wei-Yu Chen, Philip Yu-Shuan Chung, Hsiu-Jen Lin, Ching-Hua Hsieh, Chen-Hua Yu
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Patent number: 11640954Abstract: A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.Type: GrantFiled: March 31, 2021Date of Patent: May 2, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jeng-Nan Hung, Chun-Hui Yu, Kuo-Chung Yee, Yi-Da Tsai, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh