Abstract: A seal ring structure is provided. The seal ring structure includes a seal ring on a semiconductor substrate. The seal ring includes a first interconnect element and a plurality of second interconnect elements. The first interconnect element is formed on a shallow trench isolation (STI) region and a first group of P-type doping regions over the semiconductor substrate. The second interconnect elements are formed below the first interconnect element and on a second group of P-type doping regions over the semiconductor substrate. The second interconnect elements are electrically separated from the first interconnect element, and the first and second groups of P-type doping regions are separated by the STI region.

Abstract: A seal ring structure is provided. The seal ring structure includes a seal ring on a semiconductor substrate. The seal ring includes a first interconnect element and a plurality of second interconnect elements. The first interconnect element is formed on a shallow trench isolation (STI) region and a first group of P-type doping regions over the semiconductor substrate. The second interconnect elements are formed below the first interconnect element and on a second group of P-type doping regions over the semiconductor substrate. The second interconnect elements are electrically separated from the first interconnect element, and the first and second groups of P-type doping regions are separated by the STI region.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract: A method for preparing a flash memory structure comprises the steps of forming a plurality of dielectric blocks having block sidewalls on a substrate, forming a plurality of first spacers on the block sidewalls of the dielectric blocks, removing a portion of the substrate not covered by the dielectric blocks and the first spacers to form a plurality of trenches in the substrate, performing a deposition process to form an isolation dielectric layer filling the trenches, removing the dielectric blocks to expose spacer sidewalls of the first spacers, forming a plurality of second spacers on the spacer sidewalls of the first spacers, and removing a portion of the substrate not covered by the first spacers, the second spacers and the isolation dielectric layer to form a plurality of second trenches in the substrate.

Abstract: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.

Abstract: A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers.

Abstract: A novel NAND flash memory cell array and the method of fabricating the same are disclosed in this invention. The NAND flash memory cell array comprises a substrate with an active area; a plurality of cells arranged in a row on the active area; a first barrier layer covering the cells and the active area around each end of the row; a first oxide deposited to fill a gap between the cells; an oxide spacer formed along the sidewall of a cell located at each end of the row; and a poly spacer formed on the oxide spacer acting as a selection gate for driving the row of cells. The aspect ratio of the gap between the cells is about 1.8 to 3.2. Many advantages are provided with such NAND flash memory fabricating by the self-aligned process of the present invention.

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.

Abstract: A method for controlling an etching depth in a semiconductor fabricating process is provided. The method includes steps of providing a substrate having a first reflecting region and a second reflecting region, illuminating the first reflecting region and the second reflecting region with a coherence light having a wavelength &lgr; to generate an interference, performing a first etching on the second reflecting region to generate a height difference between the first reflecting region and the second reflecting region, wherein the interference intensity is changed with the first etching, and performing a second etching on the second reflecting region for a specific period of time to make the etching depth as the height difference when the interference intensity is changed to a relative extreme value.