Patents by Inventor Ching-Hwanq Su
Ching-Hwanq Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961891Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.Type: GrantFiled: March 21, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
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Patent number: 11949000Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.Type: GrantFiled: July 27, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, I-Shan Huang
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Publication number: 20240096883Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
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GATE STRUCTURE, FIN FIELD-EFFECT TRANSISTOR, AND METHOD OF MANUFACTURING FIN-FIELD EFFECT TRANSISTOR
Publication number: 20240088144Abstract: A gate structure includes a metal layer, a barrier layer, and a work function layer. The barrier layer covers a bottom surface and sidewalls of the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. The work function layer surrounds the barrier layer.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu -
Publication number: 20240021471Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.Type: ApplicationFiled: July 26, 2023Publication date: January 18, 2024Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
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Patent number: 11855098Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.Type: GrantFiled: November 14, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
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Gate structure, fin field-effect transistor, and method of manufacturing fin-field effect transistor
Patent number: 11855083Abstract: A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is surrounded by the gate dielectric layer. The metal layer is disposed over the work function layer. The barrier layer is surrounded by the work function layer and surrounds the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure.Type: GrantFiled: February 8, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu -
Publication number: 20230387230Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
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Publication number: 20230335601Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Inventors: Hsin-Yi Lee, Ya-Huei Li, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11769694Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.Type: GrantFiled: July 20, 2022Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
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Patent number: 11742395Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.Type: GrantFiled: March 28, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yi Lee, Ya-Huei Li, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11728341Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.Type: GrantFiled: March 24, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11699621Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.Type: GrantFiled: November 8, 2021Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
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Publication number: 20230207650Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Ru-Shang Hsiao, Ying Hsin Lu, Ching-Hwanq Su, Pin Chia Su, Ling-Sung Wang
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Publication number: 20230154922Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.Type: ApplicationFiled: March 17, 2022Publication date: May 18, 2023Inventors: Sung-Hsin Yang, Ru-Shang Hsiao, Ching-Hwanq Su, Chen-Bin Lin, Wen-Hsin Chan
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Publication number: 20230107945Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
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Patent number: 11616132Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.Type: GrantFiled: June 7, 2021Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Ching-Hwanq Su
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Publication number: 20230073400Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
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Patent number: 11588038Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.Type: GrantFiled: February 12, 2021Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ying Hsin Lu, Ching-Hwanq Su, Pin Chia Su, Ling-Sung Wang
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Patent number: 11563120Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: GrantFiled: October 22, 2020Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su