Abstract: A crossbar switching circuit and operating method thereof for coupling a plurality of source providers to a plurality of source consumers based on the request of the source consumer are provided. The crossbar switching circuit includes a plurality of source consumer terminals coupled to the source consumers respectively, a plurality of source provider terminals coupled to the source providers respectively, a plurality of first counters and a plurality of second counters. Wherein, each source consumer terminal has one first counter and one second counter. The first counter indicates a current latency state of the resource requested by the corresponding source consumer. The second counter indicates a current bandwidth state of resource requested by the corresponding source consumer. In addition, the connecting states between the source consumer terminals and the source provider terminals are determined based on the states of the first counters and the second counters.

Abstract: A method and apparatus to reduce the system load of motion estimation for DSP discloses circular buffers, a plurality of absolute difference calculation circuits, a multiple input adder, a full adder, a plurality of accumulators, and a control circuit. The first four bytes from the reference block buffer and the first four bytes from the search window buffer are sent to the four absolute difference calculation circuits. The control circuit determines which of the accumulators requires incrementing the value already in that accumulator by the current output of the multiple input adder. A new set of bytes from the search window buffer is then sent to the absolute difference calculation circuits, a new sum is calculated, and a second accumulator is incremented by the new sum. When all accumulators have been updated, new reference block data used. Each byte of data is loaded from memory only once.

Abstract: A crossbar switching circuit and operating method thereof for coupling a plurality of source providers to a plurality of source consumers based on the request of the source consumer are provided. The crossbar switching circuit includes a plurality of source consumer terminals coupled to the source consumers respectively, a plurality of source provider terminals coupled to the source providers respectively, a plurality of first counters and a plurality of second counters. Wherein, each source consumer terminal has one first counter and one second counter. The first counter indicates a current latency state of the resource requested by the corresponding source consumer. The second counter indicates a current bandwidth state of resource requested by the corresponding source consumer. In addition, the connecting states between the source consumer terminals and the source provider terminals are determined based on the states of the first counters and the second counters.

Abstract: An apparatus and a method of data processing system that uses multiply-accumulate instructions. The apparatus for processing data includes, a special register bank of N-bit data processing registers, a general register bank of N-bit data processing registers, a selector, a multiplier and an accumulator. The selector is coupled to the special register bank and the general register bank and is used for selecting one of the special and general register banks and outputting N-bit data from the selected register banks. The outputted N-bit data and the N-bit data held in the general register bank form a 2N-bit addition operand. The multiplier is used for performing multiply operation upon a first operand and a second operand and outputting an 2N-bit result. The accumulator is coupled to the multiplier, the selector and the general register bank and is used for performing accumulate operation upon the 2N-bit result and the 2N-bit addition operand and outputting a 2N-bit accumulated result.

Abstract: A method and apparatus to reduce the system load of motion estimation for DSP discloses circular buffers, a plurality of absolute difference calculation circuits, a multiple input adder, a full adder, a plurality of accumulators, and a control circuit. The first four bytes from the reference block buffer and the first four bytes from the search window buffer are sent to the four absolute difference calculation circuits. The control circuit determines which of the accumulators requires incrementing the value already in that accumulator by the current output of the multiple input adder. A new set of bytes from the search window buffer is then sent to the absolute difference calculation circuits, a new sum is calculated, and a second accumulator is incremented by the new sum. When all accumulators have been updated, new reference block data used. Each byte of data is loaded from memory only once.

Abstract: A method of testing cache memory is used in a memory system having a primary memory unit and a cache memory unit. The method first writes a block of test data into the cache memory unit. Then, the test data is converted by a first encoding process into a first block of encoded data. The first block if encoded data is written into the primary memory unit. Data from the primary memory unit is fetched. The fetched data from the primary memory unit is converted by a second encoding process into a second block of encoded data. The second block of encoded data is stored into the cache memory unit. Either the first block of encoded data or the second block of encoded data is compared with a predetermined block of reference data to check whether the read/write operation to the cache memory unit is normal.

Abstract: A method of selecting registers is proposed, which is used to gain access to a register in a primitive register set which is used to provide a plurality of physical registers, virtual registers, physical program counters, and virtual program counters arranged into six modes. The primitive register set is first mapped to a converted register set which contains only two modes of registers that are mapped to the six modes of registers in the primitive register set. The access to the primitive register set is carried out by a bit sequence. If Converted Mode 0 in the converted register set is selected, the selection is mapped to one of the physical registers and physical program counter in the Converted Mode 0; and if Converted Mode 1 is selected, the selection is mapped to one of the virtual registers and virtual program counter in the Converted Mode 1.

Abstract: A real-time tracing microprocessor unit and its method of operation. The microprocessor unit has a trace buffer capable of holding a plurality of trace records with each record containing a non-sequential program counter value and a state bit. When the microprocessor control unit encounters a non-sequential instruction, a program counter generator produces a non-sequential program counter value. A trace buffer controller transfers the non-sequential program counter value to a trace record having an empty state bit and sets the state bit of the trace record into an occupied state. When any one of the trace records within the trace buffer are occupied, the trace buffer controller is triggered to transfer the non-sequential program counter value to a storage device.

Abstract: A method of testing cache memory is proposed, which is designed for use on a memory system having a primary memory unit and a cache memory unit for testing the cache memory unit to check if the cache memory unit is normal in read/write operations. The proposed method comprises the steps of writing a block of test data into the cache memory unit; converting the test data through a first encoding process into a first block of encoded data; writing the first block of encoded data into the primary memory unlit; fetching data from the primary memory unit; converting the fetched data from the primary memory unit through a second encoding process into a second block of encoded data; and storing the second block of encoded data into the cache memory unit; and finally comparing either the first block of encoded data or the second block of encoded data against a predetermined block of reference data to check whether the read/write operation to the cache memory unit is normal.

Abstract: A method of determining the performance of a microprocessor during execution. The method is implemented using a microprocessor, an instruction counter and a cycle counter. First, the microprocessor is triggered into an emulation mode. The instruction counter and the cycle counter is reset to zero. Assessment points are set up along a series of instruction whose operating speed needs to be determined. The microprocessor jumps from the circuit emulation mode into a normal operating mode and then executes a series of program instructions. The instruction counter increments by one when an instruction is executed. Similarly, the cycle counter increments by one when one cycle of timing pulse is traversed. When an assessment point is encountered during instruction execution, the microprocessor jumps from the normal operating mode back into the circuit emulation mode. Microprocessor performance is evaluated by dividing the value inside the cycle counter by the value inside the instruction counter.

Abstract: A method of selecting registers is proposed, which is used to gain access to a register in a primitive register set which is used to provide a plurality of physical registers, virtual registers, physical program counters, and virtual program counters arranged into six modes. The primitive register set is first mapped to a converted register set which contains only two modes of registers that are mapped to the six modes of registers in the primitive register set. The access to the primitive register set is carried out by a bit sequence. If Converted Mode 0 in the converted register set is selected, the selection is mapped to one of the physical registers and physical program counter in the Converted Mode 0; and if Converted Mode 1 is selected, the selection is mapped to one of the virtual registers and virtual program counter in the Converted Mode 1.

Abstract: A data processing apparatus for executing multiple instruction sets.

Abstract: A simple and efficient serial interface transmission structure according to the invention comprises only 8 modes by which all required operations provided by the conventional serial interface are readily accomplished. Furthermore, a serial interface transmission structure according to the invention has the advantages of requiring a minimal amount of logic devices and input/output pins, being capable of automatically returning to an IDLE mode, being able to easily read/write data from/to devices which are connected thereto, and being able to continuously poll the status messages of the devices.