Patents by Inventor Ching-Lang Chiang

Ching-Lang Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6743703
    Abstract: A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: June 1, 2004
    Assignee: APD Semiconductor, Inc.
    Inventors: Vladimir Rodov, Paul Chang, Jianren Bao, Wayne Y. W. Hsueh, Arthur Ching-Lang Chiang, Geeng-Chuan Chern
  • Patent number: 6731327
    Abstract: Vibration damping apparatus for vibrating environment such as a light emission microscope and an integrated circuit test head includes a rigid member with remotely controlled clamping apparatus attached to spaced portions of the member. The clamping apparatus engage the microscope and the test head for reducing vibrations, and the clamping apparatus can be readily deactivated for moving the microscope or the test head for alignment purposes. Advantageously, two or more rigid members including pneumatic cylinders can be positioned around the device under test while permitting the use of mechanical probes for engaging nodes of an integrated circuit for test purposes.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: May 4, 2004
    Assignee: Hypervision, Inc.
    Inventors: Thomas Joseph Kujawa, Ching-Lang Chiang, Neeraj Khurana, Prasad Sabbineni, Daniel T. Hurley
  • Patent number: 6515330
    Abstract: A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: February 4, 2003
    Assignee: APD Semiconductor, Inc.
    Inventors: Gary M. Hurtz, Vladimir Rodov, Geeng-Chuan Chern, Paul Chang, Ching-Lang Chiang
  • Publication number: 20030006473
    Abstract: A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.
    Type: Application
    Filed: September 9, 2002
    Publication date: January 9, 2003
    Applicant: APD Semiconductor, Inc.
    Inventors: Vladimir Rodov, Paul Chang, Jianren Bao, Wayne Y.W. Hsueh, Arthur Ching-Lang Chiang, Geeng-Chuan Chern
  • Patent number: 6420225
    Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: July 16, 2002
    Assignee: APD Semiconductor, Inc.
    Inventors: Paul Chang, Vladimir Rodov, Geeng-Chuan Chern, Charles Lin, Ching-Lang Chiang
  • Patent number: 5475316
    Abstract: An emission microscope is mounted on a transportable structure for use on a test floor and encloses or garages an entire automatic test equipment head to facilitate high-speed testing. Test procedures allow development of static/fixed defects over time. A video mask can be developed based on emission sites on known good devices so that only emission from defect sites of bad devices under test are shown.
    Type: Grant
    Filed: December 27, 1993
    Date of Patent: December 12, 1995
    Assignee: Hypervision, Inc.
    Inventors: Daniel T. Hurley, Ching-Lang Chiang, Neeraj Khurana