Patents by Inventor Ching-Pin Hsu
Ching-Pin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848253Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: GrantFiled: November 8, 2021Date of Patent: December 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Publication number: 20220068766Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: ApplicationFiled: November 8, 2021Publication date: March 3, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Patent number: 11205609Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: GrantFiled: March 31, 2020Date of Patent: December 21, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Publication number: 20210242110Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: ApplicationFiled: March 31, 2020Publication date: August 5, 2021Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Patent number: 10658173Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.Type: GrantFiled: July 18, 2018Date of Patent: May 19, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Ching-Pin Hsu
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Publication number: 20200020524Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.Type: ApplicationFiled: July 18, 2018Publication date: January 16, 2020Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Ching-Pin Hsu
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Patent number: 10290919Abstract: An electronic device is provided, including a display module, an input module, a hinge module, and an antenna. The hinge module connects the display module and the input module and has a first side and an opposite second side. The antenna is disposed in the hinge module and is situated on the first side. When the display module is rotated with respect to the input module, the hinge module forces the antenna to move from the first side to the second side.Type: GrantFiled: September 29, 2017Date of Patent: May 14, 2019Assignee: WISTRON CORP.Inventors: Yu Chen Hsu, Ching Pin Hsu, Chien An Chou
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Publication number: 20190006736Abstract: An electronic device is provided, including a display module, an input module, a hinge module, and an antenna. The hinge module connects the display module and the input module and has a first side and an opposite second side. The antenna is disposed in the hinge module and is situated on the first side. When the display module is rotated with respect to the input module, the hinge module forces the antenna to move from the first side to the second side.Type: ApplicationFiled: September 29, 2017Publication date: January 3, 2019Inventors: Yu Chen Hsu, Ching Pin Hsu, Chien An Chou
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Patent number: 9337084Abstract: The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first region and a second region are defined on the first dielectric layer respectively, at least two cutting hard masks are formed and disposed within the first region and the second region respectively, at least two step-height portions disposed right under the cutting hard masks respectively. Afterwards, at least one first slot opening within the first region is formed, where the first slot opening partially overlaps the cutting hard mask and directly contacts the cutting hard mask, and at least one second contact opening is formed within the second region, where the second contact opening does not contact the cutting hard mask directly, and at least two contact holes are formed, where each contact hole penetrates through each step height portion.Type: GrantFiled: September 6, 2015Date of Patent: May 10, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chieh-Te Chen, Feng-Yi Chang, Kun-Yuan Liao, Chun-Lung Chen, Ching-Pin Hsu, Shang-Yuan Tsai
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Patent number: 9023708Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.Type: GrantFiled: April 19, 2013Date of Patent: May 5, 2015Assignee: United Microelectronics Corp.Inventors: Li-Chiang Chen, Jiunn-Hsiung Liao, Hsuan-Hsu Chen, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai, Ching-Pin Hsu
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Publication number: 20140315365Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.Type: ApplicationFiled: April 19, 2013Publication date: October 23, 2014Applicant: United Microelectronics Corp.Inventors: Li-Chiang Chen, Jiunn-Hsiung Liao, Hsuan-Hsu Chen, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai, Ching-Pin Hsu
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Patent number: 8785283Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.Type: GrantFiled: December 5, 2012Date of Patent: July 22, 2014Assignee: United Microelectronics Corp.Inventors: Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Ching-Pin Hsu
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Publication number: 20140154852Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Ching-Pin Hsu
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Patent number: 8691659Abstract: A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.Type: GrantFiled: October 26, 2011Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Pin Hsu, Yi-Po Lin, Jiunn-Hsiung Liao, Chieh-Te Chen, Feng-Yi Chang, Shang-Yuan Tsai, Li-Chiang Chen
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Publication number: 20140038399Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask. Before forming the hard mask, a gate which includes a contact etch stop layer and a dielectric layer is formed on the semiconductor substrate.Type: ApplicationFiled: October 16, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Feng-Yi Chang, Yi-Po Lin, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chih-Wen Feng, Shui-Yen Lu, Ching-Pin Hsu
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Patent number: 8592321Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask.Type: GrantFiled: June 8, 2011Date of Patent: November 26, 2013Assignee: United Microelectronics Corp.Inventors: Feng-Yi Chang, Yi-Po Lin, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chih-Wen Feng, Shui-Yen Lu, Ching-Pin Hsu
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Publication number: 20130109151Abstract: A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Inventors: Ching-Pin Hsu, Yi-Po Lin, Jiunn-Hsiung Liao, Chieh-Te Chen, Feng-Yi Chang, Shang-Yuan Tsai, Li-Chiang Chen
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Publication number: 20120315748Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Inventors: Feng-Yi Chang, Yi-Po Lin, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chih-Wen Feng, Shui-Yen Lu, Ching-Pin Hsu
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Patent number: 8252650Abstract: A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.Type: GrantFiled: April 22, 2011Date of Patent: August 28, 2012Assignee: United Microelectronics Corp.Inventors: Feng-Yi Chang, Yi-Po Lin, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chih-Wen Feng, Shui-Yen Lu, Ching-Pin Hsu
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Patent number: 6898030Abstract: A camera lens includes a barrel, a first lens, a second lens and an optical filter module. The barrel includes a first container and a diaphragm. The first lens is disposed in the first container next to the diaphragm. The second lens is disposed in the first container with a distance from the first lens. The optical filter module is disposed in the first container between the first and the second lenses.Type: GrantFiled: June 17, 2004Date of Patent: May 24, 2005Assignee: Prodisc Technology Inc.Inventors: Jui-Hsin Lin, Ching-Pin Hsu