Patents by Inventor Ching-Rong Chang
Ching-Rong Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160133213Abstract: A liquid crystal display and a driving method of the same are provided, and which drive scanning lines and data lines by a timing controller. When writing data signals to a liquid crystal capacitor, the timing controller controls a source driving circuit to provide the data signals to each data line, and control a gate driving circuit to generate a high-voltage signal to each scanning line in sequence. The high-voltage signals of two adjacent scanning lines overlap. When the high-voltage signals overlap, the timing controller transmits the data signal to each liquid crystal capacitor sequentially. After finishing writing data signals to the liquid crystal capacitor, the timing controller controls the gate driving circuit to generate a pulse signal to each scanning line continuously. The pulse signals generated by the scanning lines do not overlap. Accordingly, it can avoid the leakage of data signal stored in the liquid crystal capacitors.Type: ApplicationFiled: February 12, 2015Publication date: May 12, 2016Inventors: BOU-CHING FUNG, CHING-RONG CHANG
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Publication number: 20150048879Abstract: A bandgap reference voltage circuit comprises a current mirror unit, an operation amplifier (OP), a first resistor, a second resistor, an auxiliary unit, and a voltage generation circuit. An output end of the OP is coupled to a feedback end of the current mirror unit. An end of the first resistor and an end of the second resistor are coupled to a positive input end of the OP. Another end of the first resistor is coupled to a second end of the current mirror unit. A second end of the voltage generation circuit is coupled to another end of the second resistor. An end of the auxiliary unit is coupled to a negative input end of the OP and a first end of the voltage generation circuit, and another end of the auxiliary unit is coupled to the first end of the current mirror unit.Type: ApplicationFiled: December 18, 2013Publication date: February 19, 2015Applicant: ILI TECHNOLOGY CORP.Inventors: BOU-CHING FUNG, CHING-RONG CHANG
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Patent number: 7777530Abstract: A comparator module applied to a voltage level clamping circuit which can be implemented in an integrated circuit (IC) is provided. The IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module and a comparator module. The comparator module has an output terminal, a first input terminal coupled to a first voltage source, and a second input terminal coupled to a second voltage source. The comparator module includes a current source module, a first voltage level adjusting circuit module, a second voltage level adjusting circuit module, and a comparing circuit module.Type: GrantFiled: February 24, 2009Date of Patent: August 17, 2010Assignee: ILI Technology Corp.Inventors: Yen-Hui Wang, Ching-Rong Chang
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Patent number: 7656217Abstract: A voltage level clamping circuit which can be implemented in an integrated circuit (IC) and a high-speed comparator module, wherein the IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module coupled between the first voltage source and the second voltage source and a comparator module having an output terminal coupled to the switch module, a first input terminal coupled to the first voltage source, and a second input terminal coupled to the second voltage source, for comparing a voltage level of the first voltage source with a voltage level of the second voltage source to generate an output signal, and transmitting the output signal to the switch module to control a conducting state of the switch module to selectively clamp the voltage level of the second voltage source.Type: GrantFiled: November 5, 2007Date of Patent: February 2, 2010Assignee: ILI Technology Corp.Inventors: Yen-Hui Wang, Ching-Rong Chang
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Publication number: 20090153195Abstract: A comparator module applied to a voltage level clamping circuit which can be implemented in an integrated circuit (IC) is provided. The IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module and a comparator module. The comparator module has an output terminal, a first input terminal coupled to a first voltage source, and a second input terminal coupled to a second voltage source. The comparator module includes a current source module, a first voltage level adjusting circuit module, a second voltage level adjusting circuit module, and a comparing circuit module.Type: ApplicationFiled: February 24, 2009Publication date: June 18, 2009Inventors: Yen-Hui Wang, Ching-Rong Chang
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Publication number: 20090115460Abstract: A voltage level clamping circuit which can be implemented in an integrated circuit (IC) and a high-speed comparator module, wherein the IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module coupled between the first voltage source and the second voltage source and a comparator module having an output terminal coupled to the switch module, a first input terminal coupled to the first voltage source, and a second input terminal coupled to the second voltage source, for comparing a voltage level of the first voltage source with a voltage level of the second voltage source to generate an output signal, and transmitting the output signal to the switch module to control a conducting state of the switch module to selectively clamp the voltage level of the second voltage source.Type: ApplicationFiled: November 5, 2007Publication date: May 7, 2009Inventors: Yen-Hui Wang, Ching-Rong Chang
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Patent number: 7034573Abstract: A level shifter has a current mirror and a set of oppositely driven NMOS switch. A voltage holding module is added to help an output of the level shifter to work with a full-swing fashion. Additionally, a DC current switch is used to eliminate a DC current.Type: GrantFiled: April 14, 2005Date of Patent: April 25, 2006Assignee: Infineon-Admtek Co., Ltd.Inventor: Ching-Rong Chang
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Publication number: 20060071686Abstract: A level shifter has a current mirror and a set of oppositely driven NMOS switch. A voltage holding module is added to help an output of the level shifter to work with a full-swing fashion. Additionally, a DC current switch is used to eliminate a DC current.Type: ApplicationFiled: April 14, 2005Publication date: April 6, 2006Inventor: Ching-Rong Chang
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Patent number: 6492839Abstract: A low power dynamic logic circuit. By shifting a discharge NMOS transistor of a conventional dynamic logic circuit between an output terminal and a logic block, plus an additional charge and discharge control, the operation speed and power consumption of a dynamic circuit can be effectively improved. Using the charge redistribution to speed up the circuit operation and to reduce the body effect that affects the operation speed, the speed of the novel dynamic logic circuit is enhanced. By transferring the lump capacitor of the charge/discharge, the dynamic power can be effectively reduced. The lower power dynamic logic circuit can be used independently or combined with a conventionally dynamic logic circuit.Type: GrantFiled: May 11, 2001Date of Patent: December 10, 2002Assignee: National Chung Cheng UniversityInventors: Jinn-Shyan Wang, Ching-Rong Chang, Ching-Wei Yeh
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Publication number: 20020167335Abstract: A low power dynamic logic circuit. By shifting a discharge NMOS transistor of a conventional dynamic logic circuit between an output terminal and a logic block, plus an additional charge and discharge control, the operation speed and power consumption of a dynamic circuit can be effectively improved. Using the charge redistribution to speed up the circuit operation and to reduce the body effect that affects the operation speed, the speed of the novel dynamic logic circuit is enhanced. By transferring the lump capacitor of the charge/discharge, the dynamic power can be effectively reduced. The lower power dynamic logic circuit can be used independently or combined with a conventionally dynamic logic circuit.Type: ApplicationFiled: May 11, 2001Publication date: November 14, 2002Inventors: Jinn-Shyan Wang, Ching-Rong Chang, Ching-Wei Yeh
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Patent number: 6433577Abstract: An assembling method for a low-power programmable logic array circuit. The assembling method is capable of reducing delays and unnecessary power consumption. According to the low potential power loss when the dynamic gates in the AND-plane and the OR-plane output a low potential, the high potential power loss when the dynamic gates in the AND-plane and the OR-plane output a high potential and the probability of the dynamic gates outputting a high potential, a selection between new dynamic logic circuit and conventional dynamic circuit is carried out.Type: GrantFiled: August 17, 2001Date of Patent: August 13, 2002Assignee: National Chung Cheng UniversityInventors: Jinn-Shyan Wang, Ching-Rong Chang, Ching-Wei Yeh
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Patent number: 6157562Abstract: The invention relates to a ROM with four-phase dynamic circuits, featuring at a concept of four-phase operation by fusing and combining pseudo-domino dynamic circuits as well as skill of HS-PDCMOS dynamic circuits. Meanwhile, the invention has improved HS-PDCMOS concept circuit for use in a ROM. Analysis and simulation reveal that the invention is advantageous not only in keeping a compact circuit area but also in evaluation speed and in reducing power dissipation for a ROM.Type: GrantFiled: December 11, 1998Date of Patent: December 5, 2000Assignee: National Science Council of Republic of ChinaInventors: Jinn-Shyan Wang, Ching-Rong Chang