Patents by Inventor Ching-Tzu Chen
Ching-Tzu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11177432Abstract: A synapse device includes a perpendicularly magnetized ferrimagnetic racetrack layer, a tunneling barrier layer disposed on the racetrack layer and a reference layer including a perpendicular magnetic alloy. The racetrack layer, the tunneling layer and the reference layer have a channel portion and contact pad portions. First and second contacts are provided over the contact pad portions, and a third contact is provided over the channel portion, wherein the first and second contacts are electrically isolated from the third contact.Type: GrantFiled: June 7, 2018Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Tzu Chen, See-Hun Yang
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OPTIMIZED HIERARCHICAL SCRATCHPADS FOR ENHANCED ARTIFICIAL INTELLIGENCE ACCELERATOR CORE UTILIZATION
Publication number: 20210248072Abstract: Various embodiments are provided for optimized placement of data structures in a hierarchy of memory in a computing environment. One or more data structures may be placed in a first scratchpad memory, a second scratchpad memory, an external memory, or a combination thereof in the hierarchy of memory according to a total memory capacity and bandwidth, a level of reuse of the one or more data structures, a number of operations that use each of the one or more data structures, a required duration each the one or more data structures are required to be placed a first scratchpad or a second scratchpad, and characteristics of those of the one or more data structures competing for placement in the hierarchy of memory that are able to co-exist at a same time step. The second scratchpad memory is positioned between the external memory and the first scratchpad memory at one or more intermediary layers.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Arvind KUMAR, Swagath VENKATARAMANI, Ching-Tzu CHEN -
Publication number: 20190378973Abstract: A synapse device includes a perpendicularly magnetized ferrimagnetic racetrack layer, a tunneling barrier layer disposed on the racetrack layer and a reference layer including a perpendicular magnetic alloy. The racetrack layer, the tunneling layer and the reference layer have a channel portion and contact pad portions. First and second contacts are provided over the contact pad portions, and a third contact is provided over the channel portion, wherein the first and second contacts are electrically isolated from the third contact.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Inventors: Ching-Tzu Chen, See-Hun Yang
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Patent number: 10079355Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.Type: GrantFiled: June 5, 2017Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Patent number: 9960345Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.Type: GrantFiled: February 8, 2017Date of Patent: May 1, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Patent number: 9935283Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.Type: GrantFiled: August 12, 2016Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Publication number: 20170271602Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Patent number: 9728733Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.Type: GrantFiled: August 12, 2016Date of Patent: August 8, 2017Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Publication number: 20170148875Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Inventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Patent number: 9601685Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.Type: GrantFiled: June 15, 2016Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Publication number: 20160351679Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.Type: ApplicationFiled: August 12, 2016Publication date: December 1, 2016Inventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Publication number: 20160351840Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.Type: ApplicationFiled: August 12, 2016Publication date: December 1, 2016Inventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Patent number: 9484469Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.Type: GrantFiled: December 16, 2014Date of Patent: November 1, 2016Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Patent number: 9406872Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.Type: GrantFiled: November 16, 2015Date of Patent: August 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Publication number: 20160172507Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.Type: ApplicationFiled: December 16, 2014Publication date: June 16, 2016Inventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Publication number: 20140151770Abstract: A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Tzu Chen, Marcin J. Gajek, Simone Raoux
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Publication number: 20140151771Abstract: A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer.Type: ApplicationFiled: August 13, 2013Publication date: June 5, 2014Applicant: International Business Machines CorporationInventors: Ching-Tzu Chen, Marcin J. Gajek, Simone Raoux
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Patent number: 8624223Abstract: A graphene-based electrically tunable nanoconstriction device and a non-transitory tangible computer readable medium encoded with a program for fabricating the device that includes a back-gate dielectric layer over a conductive substrate are described. The back-gate dielectric layer may be hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts formed over a portion of the graphene layer include at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between at least one source contact, at least one the drain contact and at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer.Type: GrantFiled: November 5, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Ching-tzu Chen, Shu-Jen Han
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Patent number: 8623717Abstract: A method to fabricate a novel graphene based, electrically tunable, nanoconstriction device is described. The device includes a back-gate dielectric layer formed over a conductive substrate. The back-gate dielectric layer is, in one example, hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts are formed over a portion of the graphene layer including at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between the at least one source contact, the at least one the drain contact and the at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer.Type: GrantFiled: June 12, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Ching-Tzu Chen, Shu-Jen Han
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Publication number: 20130330885Abstract: A method to fabricate a novel graphene based, electrically tunable, nanoconstriction device is described. The device includes a back-gate dielectric layer formed over a conductive substrate. The back-gate dielectric layer is, in one example, hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts are formed over a portion of the graphene layer including at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between the at least one source contact, the at least one the drain contact and the at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer.Type: ApplicationFiled: June 12, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Tzu CHEN, Shu-Jen HAN