Abstract: An in-cell touch control panel includes a liquid crystal layer; a top glass; a bottom glass; a plurality of driving electrodes, formed between the top glass and the liquid crystal layer; and a plurality of sensing electrodes, formed between the bottom glass and the liquid crystal layer, and perpendicular to the plurality of driving electrodes. The plurality of driving electrodes and the plurality of sensing electrodes are utilized for sensing a touch point on the in-cell touch control panel.

Abstract: A gate switch apparatus of a-Si LCDs is provided. The gate switch apparatus is suitable for switching a plurality of sub gate lines and disposed in two rim spaces of a display to make a-Si TFT switch with less impedance. According to a switch driving timing, a plurality of sub gate lines are able to share a single gate line, which saves cost and reduces the difficulty in the manufacturing process.

Abstract: A method for driving an LCD monitor includes providing a common-voltage signal having a level conversion during each frame duration, dividing each frame duration into a first sub-frame duration and a second sub-frame duration according to a position having the level conversion of the common-voltage signal, driving a first set of pixel units during the first sub-frame duration according to a level of the common-voltage signal within the first sub-frame duration, and driving a second set of pixel units during the second sub-frame duration according to a level of the common-voltage signal within the second sub-frame duration.

Abstract: A gate driving device comprises a control circuit, a shift register circuit, a level shifter, a buffer block and a current overdrive protection device. The control circuit receives and outputs the logic control signals. The shift register circuit receives the logic control signals and sequentially outputs N horizontal low-voltage pulse signals from the first to Nth horizontal lines. The level shifter receives and transforms the horizontal low-voltage pulse signals into positive/negative high-voltage signals. The buffer block receives the horizontal positive/negative high-voltage signals and buffers the driving of the output level device. The current overdrive protection device receives the logic control signal and the horizontal low-voltage pulse signals. The current overdrive protection device, while being properly triggered, outputs the reset signal to prevent the sudden current spike. Accordingly, the damage of the gate driving device is avoided.

Abstract: A method of layout of a driving chip of an LCD, for reducing a size of the LCD, includes forming a first pin group including a plurality of pins utilized for outputting gate driving signals along a first direction, forming a second pin group including a plurality of pins utilized for outputting gate driving signals along the first direction, forming a first wire group including a plurality of wires each coupled between a pin of the first pin group and a panel of the LCD, and forming a second wire group including a plurality of wires each coupled between a pin of the second pin group and the panel, wherein each wire of the second wire group includes at least a bender formed inside the driving chip.

Abstract: A gate switch apparatus of a-Si LCDs is provided. The gate switch apparatus is suitable for switching a plurality of sub gate lines and disposed in two rim spaces of a display to make a-Si TFT switch with less impedance. According to a switch driving timing, a plurality of sub gate lines are able to share a single gate line, which saves cost and reduces the difficulty in the manufacturing process.

Abstract: A gate switch apparatus of a-Si LCDs is provided. The gate switch apparatus is suitable for switching a plurality of sub gate lines and disposed in two rim spaces of a display to make a-Si TFT switch with less impedance. According to a switch driving timing, a plurality of sub gate lines are able to share a single gate line, which saves cost and reduces the difficulty in the manufacturing process.

Abstract: A latchable voltage level shifter is provided. The latchable voltage level shifter comprises: a voltage level shifter receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and a high voltage flip-flop, coupled to the voltage level shifter, receiving the high voltage signal and a second phase control signal, the high voltage flip-flop latching the high voltage signal according to a timing sequence of the second phase control signal and outputting a high voltage output signal. The latchable voltage level shifter can be used in a source drive circuit so as to reduce the layout area and production cost.

Abstract: A method of layout of a driving chip of an LCD, for reducing a size of the LCD, includes forming a first pin group including a plurality of pins utilized for outputting gate driving signals along a first direction, forming a second pin group including a plurality of pins utilized for outputting gate driving signals along the first direction, forming a first wire group including a plurality of wires each coupled between a pin of the first pin group and a panel of the LCD, and forming a second wire group including a plurality of wires each coupled between a pin of the second pin group and the panel, wherein each wire of the second wire group includes at least a bender formed inside the driving chip.

Abstract: A method for driving an LCD monitor includes providing a common-voltage signal having a level conversion during each frame duration, dividing each frame duration into a first sub-frame duration and a second sub-frame duration according to a position having the level conversion of the common-voltage signal, driving a first set of pixel units during the first sub-frame duration according to a level of the common-voltage signal within the first sub-frame duration, and driving a second set of pixel units during the second sub-frame duration according to a level of the common-voltage signal within the second sub-frame duration.

Abstract: An internal resistor device of an integrated circuit chip, including a MOS transistor and a logic unit, is provided. The MOS transistor has a drain coupled to an input pin of the integrated circuit chip and a source coupled to a predetermined voltage. The logic unit receives a control signal from the input pin and a driving signal, and then executes a logic operation of the driving and the control signals. The result of the logic operation is provided to the gate of the MOS transistor. When the input pin is floating, the internal resistor device provides a predetermined fixed voltage to internal circuits chip. When the input voltage level is inverse to the predetermined fixed voltage, static current is almost not consumed.

Abstract: A display device and a gray-scale voltage generating device for the display device are provided. The gray-scale voltage generating device includes a reference voltage source, a curve-shifting control unit, and a gray-scale voltage output unit. By correcting the output voltage of the curve-shifting control unit, the devices are able to shift the Gamma curve of the gray-scale voltage output unit. Therefore, the original Gamma curve can be shifted without having distortion.

Abstract: A latchable voltage level shifter is provided. The latchable voltage level shifter comprises: a voltage level shifter receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and a high voltage flip-flop, coupled to the voltage level shifter, receiving the high voltage signal and a second phase control signal, the high voltage flip-flop latching the high voltage signal according to a timing sequence of the second phase control signal and outputting a high voltage output signal. The latchable voltage level shifter can be used in a source drive circuit so as to reduce the layout area and production cost.

Abstract: A gate switch apparatus of a-Si LCDs is provided. The gate switch apparatus is suitable for switching a plurality of sub gate lines and disposed in two rim spaces of a display to make a-Si TFT switch with less impedance. According to a switch driving timing, a plurality of sub gate lines are able to share a single gate line, which saves cost and reduces the difficulty in the manufacturing process.

Abstract: A touch screen liquid crystal display (LCD) device is provided. In its design, a LCD panel and an input panel are integrated, to prevent damages or impurity contamination in the manufacturing and assembly process of the LCD, further to spare the additional analog-to digital converter and control circuit. With the driving method of the present invention, the touch screen LCD device with integrated display and input function doesn't affect the original LCD display function. Moreover, the simple on/off driving mode also enhances the resolution requirement of the touch screen LCD.

Abstract: A voltage level shifter is provided. The shifter includes an AND gate for generating a synchronizing signal according to a periodic signal and a primitive input signal. The synchronizing signal and a first periodic control signal that are in phase with the periodic control signal are inputted to a transistor device. The transistor device is constructed with an inverter. The voltage level shifter further includes a buffer for generating an output signal and a capacitor for storing a signal. The present invention also provides a switching circuit for preventing the turning on of both PMOS transistor and NMOS transistor simultaneously during a switching status. The present invention can also solve the issue caused by the ratio of the channel width to the channel length, thus the uncertainty of the manufacturing process will not affect the circuit. Therefore, the power consumption, the chip area and the cost are reduced.

Abstract: A gate driving device comprises a control circuit, a shift register circuit, a level shifter, a buffer block and a current overdrive protection device. The control circuit receives and outputs the logic control signals. The shift register circuit receives the logic control signals and sequentially outputs N horizontal low-voltage pulse signals from the first to Nth horizontal lines. The level shifter receives and transforms the horizontal low-voltage pulse signals into positive/negative high-voltage signals. The buffer block receives the horizontal positive/negative high-voltage signals and buffers the driving of the output level device. The current overdrive protection device receives the logic control signal and the horizontal low-voltage pulse signals. The current overdrive protection device, while being properly triggered, outputs the reset signal to prevent the sudden current spike. Accordingly, the damage of the gate driving device is avoided.

Abstract: A latchable voltage level shifter is provided. The latchable voltage level shifter comprises: a voltage level shifter receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and a high voltage flip-flop, coupled to the voltage level shifter, receiving the high voltage signal and a second phase control signal, the high voltage flip-flop latching the high voltage signal according to a timing sequence of the second phase control signal and outputting a high voltage output signal. The latchable voltage level shifter can be used in a source drive circuit so as to reduce the layout area and production cost.

Abstract: A voltage level shifter is provided. The shifter includes an AND gate for generating a synchronizing signal according to a periodic signal and a primitive input signal. The synchronizing signal and a first periodic control signal that are in phase with the periodic control signal are inputted to a transistor device. The transistor device is constructed with an inverter. The voltage level shifter further includes a buffer for generating an output signal and a capacitor for storing a signal. The present invention also provides a switching circuit for preventing the turning on of both PMOS transistor and NMOS transistor simultaneously during a switching status. The present invention can also solve the issue caused by the ratio of the channel width to the channel length, thus the uncertainty of the manufacturing process will not affect the circuit. Therefore, the power consumption, the chip area and the cost are reduced.