Abstract: A method for estimating a flight time of a hydrogen fuel cell UAV (unmanned aerial vehicle) includes multiple steps performed by a controller: obtaining an internal pressure of a hydrogen tank by a pressure sensor installed on the hydrogen tank, calculating a remaining hydrogen volume according to the internal pressure and a capacity of the hydrogen tank, obtaining a reaction current value of the fuel cell, calculating a first hydrogen consumption rate according to the reaction current value, the number of a set of membrane electrodes connected in series and a Faraday constant, obtaining a second hydrogen consumption rate of a purge operation of an anode of the full cell; obtaining a hydrogen leakage rate of a stack of the fuel cell, and calculating the flight time according to the remaining hydrogen volume, the first hydrogen consumption rate, the second hydrogen consumption rate and the hydrogen leakage rate.

Abstract: A method of manipulating droplet in a programmable EWOD microelectrode array comprising multiple microelectrodes, comprising: constructing a bottom plate with multiple microelectrodes on a top surface of a substrate covered by a dielectric layer; the microelectrode coupled to at least one grounding elements of a grounding mechanism, a hydrophobic layer on the top of the dielectric layer and the grounding elements; manipulating the multiple microelectrodes to configure a group of configured-electrodes to generate microfluidic components and layouts with selected shapes and sizes, comprising: a first configured-electrode with multiple microelectrodes arranged in array, and at least one second adjacent configured-electrode adjacent to the first configured-electrode, the droplet disposed on the top of the first configured-electrode and overlapped with a portion of the second adjacent-configured-electrode; and manipulating one or more droplets among multiple configured-electrodes by sequentially activating and de-

Abstract: Disclosed herein is a device A device of the microelectrode array architecture, comprising: (a) a bottom plate comprising an array of multiple microelectrodes disposed on a top surface of a substrate covered by a dielectric layer; wherein each of the microelectrode is coupled to at least one grounding elements of a grounding mechanism, wherein a hydrophobic layer is disposed on the top of the dielectric layer and the grounding elements to make hydrophobic surfaces with the droplets; (b) a field programmability mechanism for programming a group of configured-electrodes to generate microfluidic components and layouts with selected shapes and sizes; and, (c) a system management unit, comprising: (i) a droplet manipulation unit; and (ii) a system control unit.

Abstract: The system relates to filed-programmable lab-on-chip (FPLOC) microfluidic operations, fabrications, and programming based on Microelectrode Array Architecture are disclosed herein. The FPLOC device by employing the microelectrode array architecture may include the following: (a) a bottom plate comprising an array of multiple microelectrodes disposed on a top surface of a substrate covered by a dielectric layer; wherein each of the microelectrode is coupled to at least one grounding elements of a grounding mechanism, wherein a hydrophobic layer is disposed on the top of the dielectric layer and the grounding elements to make hydrophobic surfaces with the droplets; (b) a field programmability mechanism for programming a group of configured-electrodes to generate microfluidic components and layouts with selected shapes and sizes; and, (c) a FPLOC functional block, comprising: (i) I/O ports; (ii) a sample preparation unit; (iii) a droplet manipulation unit; (iv) a detection unit; and (iv) a system control unit.

Abstract: The system relates to filed-programmable lab-on-chip (FPLOC) microfluidic operations, fabrications, and programming based on Microelectrode Array Architecture are disclosed herein. The FPLOC device by employing the microelectrode array architecture may include the following: (a) a bottom plate comprising an array of multiple microelectrodes disposed on a top surface of a substrate covered by a dielectric layer; wherein each of the microelectrode is coupled to at least one grounding elements of a grounding mechanism, wherein a hydrophobic layer is disposed on the top of the dielectric layer and the grounding elements to make hydrophobic surfaces with the droplets; (b) a field programmability mechanism for programming a group of configured-electrodes to generate microfluidic components and layouts with selected shapes and sizes; and, (c) a FPLOC functional block, comprising: (i) I/O ports; (ii) a sample preparation unit; (iii) a droplet manipulation unit; (iv) a detection unit; and (iv) a system control unit.

Abstract: Disclosed herein is a device A device of the microelectrode array architecture, comprising: (a) a bottom plate comprising an array of multiple microelectrodes disposed on a top surface of a substrate covered by a dielectric layer; wherein each of the microelectrode is coupled to at least one grounding elements of a grounding mechanism, wherein a hydrophobic layer is disposed on the top of the dielectric layer and the grounding elements to make hydrophobic surfaces with the droplets; (b) a field programmability mechanism for programming a group of configured-electrodes to generate microfluidic components and layouts with selected shapes and sizes; and, (c) a system management unit, comprising: (i) a droplet manipulation unit; and (ii) a system control unit.

Abstract: A method of manipulating droplet in a programmable EWOD microelectrode array comprising multiple microelectrodes, comprising: constructing a bottom plate with multiple microelectrodes on a top surface of a substrate covered by a dielectric layer; the microelectrode coupled to at least one grounding elements of a grounding mechanism, a hydrophobic layer on the top of the dielectric layer and the grounding elements; manipulating the multiple microelectrodes to configure a group of configured-electrodes to generate microfluidic components and layouts with selected shapes and sizes, comprising: a first configured-electrode with multiple microelectrodes arranged in array, and at least one second adjacent configured-electrode adjacent to the first configured-electrode, the droplet disposed on the top of the first configured-electrode and overlapped with a portion of the second adjacent-configured-electrode; and manipulating one or more droplets among multiple configured-electrodes by sequentially activating and de-

Abstract: An application specific integrated circuit having an embedded microprocessor and core including a memory array, self tests at full operational speed utilizing the computational power of the embedded microprocessor for deterministic testing performed by core specific test algorithms implemented in the assembly code of the embedded microprocessor.

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.

Abstract: An integrated circuit layout technique is described which employs an optimization-driven clustering technique to provide improved cell placement. The technique utilizes clustering of cells based upon Rent's rule, with global-optimization-derived inter-cell distances being used to break ties when identical Rent exponents are encountered. A constraint on the number of cells permitted to be in a cluster and a constraint on the maximum Rent exponent which to be considered for merging clusters minimize the "overgrowth" of clusters and serve to even out cluster size, ideally suiting the technique to conventional partitioning and placement schemes.

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.