Abstract: The present invention provides a control method of an electronic device, wherein the control method includes the steps of: using a first beacon setting to transmit beacons; if a wireless communication state of the electronic device satisfies a condition, using a second beacon setting to transmit beacons; wherein the first beacon setting and the second beacon setting have different beacon periods or different payload sizes.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.

Abstract: A voltage controlled oscillator (VCO) with improved frequency characteristics is provided. The VCO includes a converting circuit supplied between a bias voltage and a ground voltage for converting the control voltage into a control current, a replica bias circuit coupled to the converting circuit for providing a swing voltage, and a ring oscillating circuit coupled to the replica bias circuit having at least two delay units coupled in series for successively delaying an input signal as the oscillating signal after a period of delay time.

Abstract: A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.

Abstract: A voltage controlled oscillator (VCO) with improved frequency characteristics is provided. The VCO includes a converting circuit supplied between a bias voltage and a ground voltage for converting the control voltage into a control current, a replica bias circuit coupled to the converting circuit for providing a swing voltage, and a ring oscillating circuit coupled to the replica bias circuit having at least two delay units coupled in series for successively delaying an input signal as the oscillating signal after a period of delay time.

Abstract: A clock and data recovery circuit generates a recovery and a reference clock corresponding to the input data and includes a phase shifter generating M discrete clocks at different phases, a data sampler generating a select signal according to the input data and the M discrete clocks, a primary phase selector outputting two consecutive discrete clocks and at least one interpolated clock with a phase between the phases of the two consecutive discrete clocks, a multiplexer selecting one of the two consecutive discrete clocks or the interpolated clock as a selected output clock, a phase detector receiving the selected output clock as the recovery clock and outputting an advanced calibration signal if the recovery clock leads or lags the input data, an advanced phase selector receiving the advanced calibration signal and transmitting the phase select signal to the multiplexer for adjusting the selected output clock and a primary calibration signal.

Abstract: An ornamental lamp has a base. A secondary light bulb is mounted on top of the base. A barrel is also mounted on top of the base and around the secondary light bulb. A bottle containing water and wax is mounted on the barrel and having a bottom end inserted into the barrel to be close to the secondary light bulb. Two rods securely stand on the base and a plate is securely mounted on top ends of the rods. Two sockets are mounted on the plate and two primary light bulbs are respectively plugged to the sockets. A shade is maintained in a position above the primary light bulbs by a pole securely connected between the plate and the shade. Therefore, by such arrangement, the ornamental lamp can be used for illumination as well as providing an ornamental effect.