Abstract: A full bisection bandwidth network, having a plurality of nodes and a plurality of paths among the nodes, is divided into a plurality of Virtual Local Area Networks (“VLANs”) by assigning paths to the VLANs such that each VLAN satisfies a spanning tree protocol and all paths are active in at least one VLAN.

Abstract: An interconnect network having a plurality of identical fabrics partitions the switching elements of the fabrics, so that many links can be combined into single cables. In the partitioning method, one or more of the switching elements from the first stage of each of the fabrics are physically packaged onto the same board called a concentrator, and these concentrators are physically distributed among the processing nodes connected to the interconnect network. The concentrator allows all the links from each processing node to a concentrator, each of which need to be connected to different fabrics, to be combined into a single cable. Furthermore, the concentrator allows all the links from a single switching element in the first stage to be combined into a single cable to be connected to the subsequent or expansion (second and higher) stages of the fabric. The subsequent or expansion stages of each fabric can be implemented independently of other fabrics in a centralized location.

Abstract: An interconnect network having a plurality of identical fabrics partitions the switching elements of the fabrics, so that many links can be combined into single cables. In the partitioning method, one or more of the switching elements from the first stage of each of the fabrics are physically packaged onto the same board called a concentrator, and these concentrators are physically distributed among the processing nodes connected to the interconnect network. The concentrator allows all the links from each processing node to a concentrator, each of which need to be connected to different fabrics, to be combined into a single cable. Furthermore, the concentrator allows all the links from a single switching element in the first stage to be combined into a single cable to be connected to the subsequent or expansion (second and higher) stages of the fabric. The subsequent or expansion stages of each fabric can be implemented independently of other fabrics in a centralized location.

Abstract: An enhanced interface between a processor and an Asynchronous Transfer Mode (ATM) segmentation controller. A software driver communicates with the controller to efficiently segment protocol data units (PDUs) into ATM cells for transmission. The software driver creates a series of data structures in memory for managing the PDU, wherein the data structures include a linked list of buffer descriptors that describe the size and location of subportions of the PDU. The ATM controller is capable of accessing and interpreting these data structures. As a result, only a single I/O operation is required for the software driver to initiate direct memory access (DMA) operations by the ATM controller to retrieve the data structures from memory and subsequently transmit the PDU.

Abstract: A system for verifying design of a digital system. A digital system, which receives input vectors and produces output vectors, is simulated. The invention generates a sequence of synthesized input vectors, and applies them to the simulated system. These input vectors cause changes in internal variables, and the output vectors. The invention also independently computes the values which internal variables and output vectors are expected to assume. The invention then compares the simulated internal and output variables with the computed values. If they agree, the simulation is assumed to function properly.

Abstract: An apparatus an method for adaptive time slot scheduling of communications traffic generated by end-point host in ATM network. The scheduler includes a time slot ring including an array of time slots, wherein each of said time slots includes a virtual channel identifier (VCID) of a virtual channel (VC) to be serviced; a VC table including an array of VC descriptors, wherein the VCID stored in said time slot ring points to a VC descriptor in the VC table; and processor for scheduling the VCs in said time slots of said time slot ring, wherein the time slots ring are circularly processed in a continuous fashion thereby enabling scheduled transmission of ATM cells in the network. The processor is operable to queue the VCID of a newly calculated target slot in an already occupied time slot if the newly calculated target slot is occupied, thereby creating a linked list of VCs, and the processor is operable to service all VCs at a single time slot before proceeding to a next time slot.