Patents by Inventor Chiung-Yu Feng

Chiung-Yu Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Common pass gate layout of a D flip flop
    Patent number: 7465970
    Abstract: A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: December 16, 2008
    Assignee: Faraday Technology Corp.
    Inventors: Jeng-Huang Wu, Chiung-Yu Feng, Chien-Chih Huang, Yu-Wen Tsai
  • Common Pass Gate Layout of a D Flip Flop
    Publication number: 20070262349
    Abstract: A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 15, 2007
    Inventors: Jeng-Huang Wu, Chiung-Yu Feng, Chien-Chih Huang, Yu-Wen Tsai