Patents by Inventor Chiyoshi Kamada
Chiyoshi Kamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7522692Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.Type: GrantFiled: March 7, 2007Date of Patent: April 21, 2009Assignee: Hitachi, Ltd.Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Patent number: 7289553Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.Type: GrantFiled: March 4, 2003Date of Patent: October 30, 2007Assignee: Hitachi, Ltd.Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Publication number: 20070153886Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.Type: ApplicationFiled: March 7, 2007Publication date: July 5, 2007Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Patent number: 7089525Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.Type: GrantFiled: October 21, 2003Date of Patent: August 8, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
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Publication number: 20040079996Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.Type: ApplicationFiled: October 21, 2003Publication date: April 29, 2004Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
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Patent number: 6662344Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.Type: GrantFiled: March 8, 2002Date of Patent: December 9, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
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Publication number: 20030169808Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.Type: ApplicationFiled: March 4, 2003Publication date: September 11, 2003Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Patent number: 6603807Abstract: An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.Type: GrantFiled: February 26, 1999Date of Patent: August 5, 2003Assignee: Hitachi, Ltd.Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Publication number: 20020149084Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.Type: ApplicationFiled: March 8, 2002Publication date: October 17, 2002Applicant: Hitachi, Ltd.Inventors: Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, Chiyoshi Kamada
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Patent number: 5616520Abstract: A semiconductor device is fabricated by forming first metal balls on electrode pads of a semiconductor chip. The first metal balls each can have a sharp tipped anchor. All of the anchors simultaneously flattened slightly only to the extent of equalizing the height thereof. The first metal balls are bonded to electrodes formed on a substrate with wirings by embedding the anchors into the electrodes. Alternatively, second metal balls can be formed on the electrodes which are then flattened to equalize the height thereof. The first metal balls, either with or without the anchors, are bonded to the second metal balls. The first and second metal balls are preferably heated during the bonding step to soften the second metal balls.Type: GrantFiled: December 30, 1994Date of Patent: April 1, 1997Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Masahiko Nishiuma, Norio Nakazato, Hiroyuki Takahashi, Chiyoshi Kamada, Motoo Suwa
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Patent number: 5523622Abstract: For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.Type: GrantFiled: September 25, 1995Date of Patent: June 4, 1996Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takashi Harada, Kazuhiro Yoshihara, Kazutaka Masuzawa, Kiyoshi Hayashi, Jun Kumazawa, Kenji Nagai, Masahiko Nishiuma, Chiyoshi Kamada
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Patent number: 5294751Abstract: A high frequency transmission line structure has a reference potential plane conductor layer, a plurality of strip line conductors, a dielectric material layer interposed between the reference potential plane conductor layer and the strip line conductors and a shielding conductor unit provided between adjacent two strip line conductors. The shielding conductor unit includes first and second slender conductor portions extending substantially in a direction parallel with a lengthwise direction of the strip line conductors and connected to be integral with each other at their first ends. The second ends of the first and second slender conductor portions being electrically connected with the reference potential plane conductor layer.Type: GrantFiled: November 13, 1991Date of Patent: March 15, 1994Assignee: Hitachi Ltd.Inventor: Chiyoshi Kamada
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Patent number: 5225709Abstract: A packaged semiconductor device has a package, a semiconductor IC chip disposed in a space formed in the package, a strip conductor buried at a first level in the package for carrying a signal to be coupled to the IC chip, a first reference potential conductor buried at a second level in the package for providing a reference potential for the IC chip and a second reference potential conductor buried at the first level in the package for shielding the strip conductor. A connection conductor such as a bonding wire is provided across the second reference potential conductor for connecting the IC chip with one of the ends of the strip conductor. A dielectric material is provided between the connection conductor and the second reference potential conductor to provide the connection conductor with a characteristic impedance matched with an impedance of a source of the signal the connection conductor carries.Type: GrantFiled: June 13, 1991Date of Patent: July 6, 1993Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Masahiko Nishiuma, Chiyoshi Kamada
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Patent number: 5140407Abstract: In a superhigh speed device driven by GHz band frequencies, a semiconductor integrated circuit device is provided, in which an adjusting impedance is arranged in the inside of a high frequency package accommodating a semiconductor chip to compensate for the mismatching between the characteristic impedance of the package wiring and the terminal impedance of the signal transmission line in the package in order to adjust the input impedance to the characteristic impedance of the signal transmission line.Type: GrantFiled: November 23, 1990Date of Patent: August 18, 1992Assignee: Hitachi, Ltd.Inventor: Chiyoshi Kamada