Patents by Inventor Chizuko Yasunobu

Chizuko Yasunobu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7549208
    Abstract: In a method of mounting a planar electronic circuit chip onto a flexible sheet together with another planar electronic element, the electronic circuit part and the another electric element are selected so that the planar surface of the another electric element is greater than the planar surface of the electronic circuit chip, and the another electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the another electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: June 23, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Sobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Publication number: 20080054427
    Abstract: A non-contact identification semiconductor device is provided with a semiconductor chip including a receiving circuit that receives an inquiry to the non-contact identification semiconductor device, a memory that stores identification information of multiple bits and a sending circuit that sends the identification information. An antenna coupled to said semiconductor chip receives the identification information from said semiconductor chip and transmits the identification information outside of said non-contact semiconductor. The long side length of the semiconductor chip is not greater than 0.5 mm in plane dimension, and the identification information is stored by a pattern printed by an electron beam.
    Type: Application
    Filed: October 23, 2007
    Publication date: March 6, 2008
    Inventors: Mitsuo USAMI, Kazutaka Tsuji, Takeshi Saito, Akira Sato, Kenji Sameshima, Kazuo Takaragi, Chizuko Yasunobu
  • Patent number: 7309019
    Abstract: A method of checking a sheet as to forgery thereof, the sheet being provided with an electronic circuit chip from or in which information can be read out or written and having visible information. The method includes a step of encrypting the visible information of the sheet and storing the encrypted visible information in the electronic circuit chip, and a step of determining discriminatively the authenticity of the sheet by comparing the visible information of the sheet with the information stored in the electronic circuit chip.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: December 18, 2007
    Assignees: Hitachi, Ltd., Hitachi Research Institute
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Patent number: 7298029
    Abstract: A non-contact identification semiconductor device is provided with a semiconductor chip including a receiving circuit that receives an inquiry to the non-contact identification semiconductor device, a memory that stores identification information of multiple bits and a sending circuit that sends the identification information. An antenna coupled to said semiconductor chip receives the identification information from said semiconductor chip and transmits the identification information outside of said non-contact semiconductor. The long side length of the semiconductor chip is not greater than 0.5 mm in plane dimension, and the identification information is stored by a pattern printed by an electron beam.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: November 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Kazutaka Tsuji, Takeshi Saito, Akira Sato, Kenji Sameshima, Kazuo Takaragi, Chizuko Yasunobu
  • Patent number: 7061083
    Abstract: This Application is intended to provide a method for effectively protecting paper or film-form media against forgery. This can be achieved by, for example, embedding in a paper or film-form medium a thin semiconductor chip up to 0.5 mm square, equipped with an antenna, and characterized in that the side walls of the semiconductor chip are formed using oxide films, and in that multiple such semiconductor chips are separated by etching. Limiting the size of these semiconductor chips to 0.5 mm or less enables improvement against bending and concentrated loads, and separating the semiconductor chips by etching results in semiconductor chips free from cracking and breakage. Also, the oxide films constituting the side walls of the semiconductor chips prevents short-circuiting at edges during connection to the respective antennas. Thus, simplified processes can be adopted.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: June 13, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Kazutaka Tsuji, Takeshi Saito, Akira Sato, Kenji Sameshima, Kazuo Takaragi, Chizuko Yasunobu
  • Publication number: 20060108412
    Abstract: A method of checking sheets as to forgery thereof, the sheet being provided with an electronic circuit chip from or in which information can be read out or written and having visible information. The method includes a step of encrypting the visible information of the sheet and storing the encrypted visible information in the electronic circuit chip, and a step of determining discriminatively the authenticity of the sheet by comparing the visible information of the sheet with the information stored in the electronic circuit chip.
    Type: Application
    Filed: January 4, 2006
    Publication date: May 25, 2006
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Patent number: 7007854
    Abstract: A method of checking sheets as to forgery thereof, the sheet being provided with an electronic circuit chip from which information can be read cut or written and having visible information. The method includes a step of encrypting the visible information of the sheet and storing the encrypted visible information in the electronic circuit chip, and a step of determining discriminatively the authenticity of the sheet by comparing the visible information of the sheet with the information stored in the electronic circuit chip.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 7, 2006
    Assignees: Hitachi, Ltd., Hitachi Research Institute
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Patent number: 6996535
    Abstract: A client is connected to a server for providing electronic commerce services in electronic commerce. An order is transmitted for a product in response to an input by a user to the server through a communications network. A trading identifier associated with the order and data on the contents of the order is received from the server, which is stored in a storage device. Associated trading processing information includes a present status of processing for processing initiated for the order, a present status of processing for delivery of the product corresponding to the order, a present status of processing for payment processing for the trading, and the trading identifier. During updating, a trading identifier is compared with trading identifiers included in the stored trading processing information, and a warning is output if they are not coincident. Updated trading processing information is added to the trading information stored in the storage device if they are coincident.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: February 7, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Ono, Chizuko Yasunobu
  • Publication number: 20050194591
    Abstract: A non-contact identification semiconductor device is provided with a semiconductor chip including a receiving circuit that receives an inquiry to the non-contact identification semiconductor device, a memory that stores identification information of multiple bits and a sending circuit that sends the identification information. An antenna coupled to said semiconductor chip receives the identification information from said semiconductor chip and transmits the identification information outside of said non-contact semiconductor. The long side length of the semiconductor chip is not greater than 0.5 mm in plane dimension, and the identification information is stored by a pattern printed by an electron beam.
    Type: Application
    Filed: April 8, 2005
    Publication date: September 8, 2005
    Inventors: Mitsuo Usami, Kazutaka Tsuji, Takeshi Saito, Akira Sato, Kenji Sameshima, Kazuo Takaragi, Chizuko Yasunobu
  • Publication number: 20040176972
    Abstract: A service information processing system includes a goods information display unit for retrieving explanation and a price of goods and explanation of financial products and transmitting them to a client terminal; a goods determination judgment unit for retrieving a working term of the financial products from a contract information DB by using identification information of the financial products selected by the client, and starting monitoring whether or not the working term of the financial products is reached; and a good determination acceptance unit for retrieving one or a plurality of goods or services purchasable by a post-working amount obtained as a result of investment of a fund corresponding to the purchase amount in the selection financial products when the working term is reached.
    Type: Application
    Filed: August 8, 2003
    Publication date: September 9, 2004
    Inventors: Kenji Baba, Chizuko Yasunobu, Haruko Yakabe, Kiyoshi Kumagai, Reki Yamamoto
  • Publication number: 20040156176
    Abstract: In a method of mounting a planar electronic circuit chip onto a flexible sheet together with another planar electronic element, the electronic circuit part and the another electric element are selected so that the planar surface of the another electric element is greater than the planar surface of the electronic circuit chip, and the another electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the another electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.
    Type: Application
    Filed: October 20, 2003
    Publication date: August 12, 2004
    Applicant: HITACHI, LTD.
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Patent number: 6731509
    Abstract: In a method of mounting a planar electronic circuit chip onto a flexible sheet together with another planar electronic element, the electronic circuit part and the another electric element are selected so that the planar surface of the another electric element is greater than the planar surface of the electronic circuit chip, and the another electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the another electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: May 4, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Sobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Publication number: 20040060978
    Abstract: A method of checking sheets as to forgery thereof, the sheet being provided with an electronic circuit chip from or in which information can be read out or written and having visible information.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 1, 2004
    Applicants: HITACHI, LTD., HITACHI RESEARCH INSTITUTE
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Publication number: 20040019519
    Abstract: An evaluating service system includes a random number generator for generating a random number for use in a simulation for predicting an operating rate of a facility, an operating rate simulation unit for predicting an operating rate, a device utilization effect calculation unit for calculating a device utilization effect from a predicted operating rate, a device utilization effect/income conversion unit for converting the device utilization effect to an income, an introduction/operation expense calculation unit for calculating costs generated by the introduction and operation of the device, a profit calculation unit for calculating a profit generated by the introduced device from the income and expense, a predicted profit storage unit for storing the result of at least two or more profit predictions, and a predicted profit display unit for displaying the result of an evaluation on a screen or printing the result for presentation.
    Type: Application
    Filed: March 27, 2003
    Publication date: January 29, 2004
    Inventors: Shigeyuki Tani, Chizuko Yasunobu, Takashi Yabutani, Hiroyuki Yagi
  • Patent number: 6659353
    Abstract: A method of checking sheets as to forgery thereof, the sheet being provided with an electronic circuit chip from which information can be read out or written and having visible information. The method includes a step of encrypting the visible information of the sheet and storing the encrypted visible information in the electronic circuit chip, and a step of determining discriminatively the authenticity of the sheet by comparing the visible information of the sheet with the information stored in the electronic circuit chip.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: December 9, 2003
    Assignees: Hitachi, Ltd., Hitachi Research Institute
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Publication number: 20030191705
    Abstract: As to investment issues which are selected by an investor as investment choices, an issue-wise investment amount which is weighted by reflecting issue-wise investment analysis information which is inputted by an analyst is calculated, and an operator incorporates quantity of issues for total investment amounts into securities.
    Type: Application
    Filed: November 22, 2002
    Publication date: October 9, 2003
    Applicant: HITACHI, LTD
    Inventors: Makoto Miyata, Hiroshi Yoshikawa, Chizuko Yasunobu, Seiji Futatsugi, Takeshi Ieshima
  • Publication number: 20020161620
    Abstract: The present invention is intended to provide a marketing system capable of organically linking an analysis result to the data of a business rule. An analysis capability of the marketing system according to the invention extracts information necessary for counterplan analysis from a shopping history database, a customer database, and a merchandise database, analyzes the extracted information, and stores an analysis result into an analysis result database. A rule generation capability of the marketing system extracts the analysis result information from the analysis result database, generates a business rule by adding rule parameter definition information of person in charge inputted from an input device to the extracted analysis result information, and stores the generated business rule into a business rule base.
    Type: Application
    Filed: February 18, 1999
    Publication date: October 31, 2002
    Inventors: SHYOKO HATANAKA, CHIZUKO YASUNOBU, MITSUO SUDO, YASUYUKI OTA, KAZUYUKI SEKIGUCHI, TAKESHI KOJIMA
  • Patent number: 5615304
    Abstract: In a judgement support system and method, essential items to be necessarily judged and optional items to be optionally judged by a user are displayed on a menu screen, thereby allowing a judgement through intuitive knowledge of the user. After judgement results of all essential items have been inputted, the system is allowed to stop its operation. When a judgement result is inputted, an evaluation of the judgement is outputted in accordance with a predetermined rule. The evaluation includes updating a judgement item. For example, an essential judgement item is added. The menu screen is dynamically changed during judgement.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: March 25, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Shyoko Hatanaka, Chizuko Yasunobu, Michitaka Kosaka
  • Patent number: 5544281
    Abstract: A method of supporting decision-making for predicting future time-series data by using measured values of time-series data stored in a storage and knowledge stored in a knowledge base. The knowledge is related to interpretation and prediction of the time-series data. A plurality of time-series data stored in the storage device is prepared in an order of time-serial points corresponding to the time-series data. Knowledge which includes reference to the time-series data using a relative time interval from the time-series data is stored to the knowledge base. One the time-serial points of the time-series data is designated. Thereafter, the relative time interval in the knowledge is subtracting from the designated time-serial point to determine the time-serial point corresponding to the time-series data, and the future time-series data is inferred by using the knowledge and the time-series data.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: August 6, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Maruoka, Chizuko Yasunobu, Tadashi Hirose, Mayumi Kida, Kouichiro Ino, Yoshiya Miyagawa
  • Patent number: 5471559
    Abstract: Fuzzy knowledge stored in a knowledge base is written into a memory. When fuzzy reasoning is executed by a fuzzy reasoning unit based on the content of the memory, a control unit in a central processing unit may modify the knowledge base in the memory. The control unit is programmed such that after it has modified the knowledge base in the memory, it causes a reasoning execution unit to repeatedly and automatically execute predetermined fuzzy reasoning by the number of times corresponding to the number of input data. The control unit also modifies the knowledge base and causes the reasoning execution unit to execute the fuzzy reasoning. By reading out the knowledge base in the memory, it is possible to verify the validity of the fuzzy knowledge without executing the simulation of the fuzzy reasoning. The fuzzy reasoning course of the reasoning execution unit may be stored in another memory.
    Type: Grant
    Filed: March 27, 1990
    Date of Patent: November 28, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Chizuko Yasunobu, Fumihiko Mori, Hiroshi Yamada, Seiji Yasunobu, Ryuko Someya