Abstract: A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced.

Abstract: A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced.

Abstract: Embodiments of the invention are directed to an exposure method for preventing wafer breakage, particularly of a trench-type power MOS device. In one embodiment, the exposure method includes: (a) providing a substrate; (b) forming a trench area and a non-trench area on the substrate; (c) carrying the substrate on a hot plate, the hot plate having a plurality of supporters corresponding to the non-trench area; and (d) performing photoresist coating and baking procedures to the substrate. The exposure method of the present invention can prevent wafer breakage due to rapid temperature variation so as to increase the yield and the efficiency of the manufacturing process and reduce the cost.

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions. The method further comprises forming a sacrificial oxide layer on the active area, removing the sacrificial oxide layer to expose the active area, and forming a gate oxide layer on the active area.

Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. A method of forming a gate oxide on a substrate comprises providing a substrate having thereon a plurality of trenches having gate oxides formed therein, wherein the plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer disposed thereon and used to form the plurality of trenches. The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions.

Abstract: The present invention provides a method for fabricating semiconductor devices, which includes the following steps. First, a silicide layer is formed on a substrate. Then, the silicide layer is defined, and an oxide layer is formed uniformly on the substrate and the silicide layer. Next, the oxide layer is etched to form a sidewall oxide layer by dry etching process, and the remaining oxide layer on the substrate is removed by wet etching. Next, inactive gas is added to the surface of the silicide layer to perform an anneal process. Finally, a mask oxide layer is formed on the silicide layer.

Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.

Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a).

Abstract: A method of contact ion implantation is disclosed. Only one mask and a dosage-enhanced implantation is utilized to form different types of doped contact regions. A blanket ion implantation is first carried out, and all the contact regions of first and second type are formed with the first conductive type impurities. Then a mask is defined to cover the first type contact regions and expose the second type regions. A second ion implantation is now carried out to implant impurity ions of second conductive type into the second type contact regions. The dosage of these second conductive type ions is determined so that, the second type contact regions are convert from the first conductive type into section conductive type.

Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a) providing a semiconductor substrate, b) forming a conductive layer on the semiconductor substrate, c) forming a dielectric layer on the conductive layer, d) forming a titanium nitride layer directly on the dielectric layer without contacting the conductive layer, and e) patternizing the titanium nitride layer, the dielectric layer and the conductive layer, wherein the dielectric layer is used for avoiding spontaneous electrochemical reaction between the titanium nitride layer and the conductive layer.

Abstract: The present invention provides a new method for making a load resistor in a semiconductor chip. According to the new method, a linear-shaped doped polysilicon layer is formed onto the surface of the semiconductor chip that comprises a Si substrate and an NSG layer. This layer functions as a conductive path. A slot is formed in this layer by removing a section from the conductive path. This slot reaches down to the NSG layer effectively cutting off the polysilicon layer. Then, a rugged polysilicon layer is evenly deposited onto the surface of the slot for connection of the conductive path. The polysilicon layer over the slot and the doped polysilicon layer defines the load resistor. The result is a high resistance value with usage of only a small space.

Abstract: The present invention is a method for increasing the refresh time of DRAM. This invention is for decreasing the stress between the bird's beak of field oxide and silicon substrate by using fluorine ion implant before field oxidation and the optimal structure of LOCOS to effectively preventing the current leakage from the bird's beak of field oxide. Therefore, this invention can increase the refresh time of DRAM and greatly enhance the performance in DRAM.

Abstract: A trenched stack-capacitor applied in a memory unit is formed through a simple process of manufacturing a stack capacitor with high density.

Abstract: The present invention provides a method for forming a bonding pad having a low contact resistance. The method includes steps of: a) forming a bonding pad structure on a substrate having a metal layer by forming a passivation layer over said metal layer and etching the passivation layer with a fluorine-containing gas by which a fluorine-containing layer is formed on a surface of said bonding pad structure; and b) removing the fluorine-containing layer for reducing a contact resistance of said bonding pad structure.

Abstract: A method of damage-free doping for forming a dynamic random access memory cell is disclosed herein. A phosphoric silicate glass is deposited as a diffusion source. The phosphorous ions of phosphoric silicate glass can be diffused into a substrate to form the source/drain regions by a high temperature during a thermal annealing process. Next, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can reduce the damage of a dynamic random access memory.