Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device is disclosed. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.

Abstract: A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.

Abstract: A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.

Abstract: A method for packaging semiconductor device assemblies. An assembly is formed which includes a semiconductor die, a tape positioned over the active surface of the die, and a substrate element positioned on an opposite side of the tape from the die. Bond pads of the die are exposed through a slot formed through the tape and an aligned opening formed through the substrate element facilitate the extension of intermediate conductive elements from the bond pads and through the slot and opening, to corresponding contact areas on the substrate element. One or both ends of the slot extend beyond an outer periphery of the die to facilitate introduction of an encapsulant material into a channel or receptacles defined by the slot, opening, and active surface of the semiconductor die. Prior to encapsulation, the side of the opening of the substrate element is sealed opposite the tape with a coverlay to contain the encapsulant material within the channel or receptacle.

Abstract: A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.

Abstract: A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.

Abstract: A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the die. The substrate includes a circuit side having a pattern of conductors and wire bonding sites, and a back side having an array of external contacts (e.g., BGA solder balls) in electrical communication with the conductors. The bonding sites on the conductors overhang the peripheral edges of the substrate such that access is provided for bonding wires to the bonding sites and to the die contacts. Because the substrate is bonded circuit side down to the die, a loop height of the wires, and an overall height (profile) of the package are reduced by a thickness of the substrate. In addition, a planarity of molded segments that encapsulate the wires is improved, and mold bleed during molding of the molded segments is reduced.

Abstract: A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the die. The substrate includes a circuit side having a pattern of conductors and wire bonding sites, and a back side having an array of external contacts (e.g., BGA solder balls) in electrical communication with the conductors. The bonding sites on the conductors overhang the peripheral edges of the substrate such that access is provided for bonding wires to the bonding sites and to the die contacts. Because the substrate is bonded circuit side down to the die, a loop height of the wires, and an overall height (profile) of the package are reduced by a thickness of the substrate. In addition, a planarity of molded segments that encapsulate the wires is improved, and mold bleed during molding of the molded segments is reduced.

Abstract: A method for packaging semiconductor device assemblies. An assembly is formed which includes a semiconductor die, a tape positioned over the active surface of the die, and a substrate element positioned on an opposite side of the tape from the die. Bond pads of the die are exposed through a slot formed through the tape and an aligned an opening formed through the substrate element facilitate the extension of intermediate conductive elements from the bond pads and through the slot and opening, to corresponding contact areas on the substrate element. One or both ends of the slot extend beyond an outer periphery of the die to facilitate introduction of an encapsulant material into a channel or receptacles defined by the slot, opening, and active surface of the semiconductor die. Prior to encapsulation, the side of the opening of the substrate element is sealed opposite the tape with a coverlay to contain the encapsulant material within the channel or receptacle.

Abstract: A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the die. The substrate includes a circuit side having a pattern of conductors and wire bonding sites, and a back side having an array of external contacts (e.g., BGA solder balls) in electrical communication with the conductors. The bonding sites on the conductors overhang the peripheral edges of the substrate such that access is provided for bonding wires to the bonding sites and to the die contacts. Because the substrate is bonded circuit side down to the die, a loop height of the wires, and an overall height (profile) of the package are reduced by a thickness of the substrate. In addition, a planarity of molded segments that encapsulate the wires is improved, and mold bleed during molding of the molded segments is reduced.

Abstract: A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the die. The substrate includes a circuit side having a pattern of conductors and wire bonding sites, and a back side having an array of external contacts (e.g., BGA solder balls) in electrical communication with the conductors. The bonding sites on the conductors overhang the peripheral edges of the substrate such that access is provided for bonding wires to the bonding sites and to the die contacts. Because the substrate is bonded circuit side down to the die, a loop height of the wires, and an overall height (profile) of the package are reduced by a thickness of the substrate. In addition, a planarity of molded segments that encapsulate the wires is improved, and mold bleed during molding of the molded segments is reduced.

Abstract: Die pads are provided which reduce moisture retention and thermal mismatch by employing a number of die pad sections or a die pad support portion with a number of relief regions. In each case, the die pad area to die area ratio is reduced to improve the thermal mismatch between the die and the die pad. Also, the die pad sections or relief regions are arranged in a spaced apart fashion to provide moisture escape paths between the die and the die pad.