Patents by Inventor Chong Lee
Chong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200381348Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.Type: ApplicationFiled: May 30, 2019Publication date: December 3, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Shun CHANG, Teck-Chong LEE
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Patent number: 10833144Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.Type: GrantFiled: November 14, 2016Date of Patent: November 10, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Hua Chen, Teck-Chong Lee
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Publication number: 20200350282Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.Type: ApplicationFiled: July 17, 2020Publication date: November 5, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Shun CHANG, Teck-Chong LEE
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Publication number: 20200335858Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.Type: ApplicationFiled: April 18, 2019Publication date: October 22, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Hua CHEN, Sheng-Chi HSIEH, Chen-Chao WANG, Teck-Chong LEE
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Publication number: 20200261779Abstract: The present disclosure relates to a golf tee, and more particularly, to a golf tee in which a portion on which a ball is placed is formed of a flexible material so as to prevent the tee from being lost or damaged by being broken or displaced due to an impact applied thereto by a golf club head when making a tee shot, and which is configured to be stably fixed and to be easily stuck into/pulled out from the ground and to maintain the initial height of the ball constant so as to reduce the inconvenience of adjusting the height of the ball whenever the tee is inserted into the ground.Type: ApplicationFiled: August 8, 2019Publication date: August 20, 2020Inventor: Tedd Chong Lee
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Patent number: 10741523Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.Type: GrantFiled: October 11, 2018Date of Patent: August 11, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Shun Chang, Teck-Chong Lee
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Publication number: 20200118970Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.Type: ApplicationFiled: October 11, 2018Publication date: April 16, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Shun CHANG, Teck-Chong LEE
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Publication number: 20200103615Abstract: An optical imaging system including a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens disposed in order from an object side, wherein one or more of the first to sixth lenses is disposed between a stop and an imaging plane and of those, one or more has positive refractive power and one is made of a glass material, and four or more of the first to sixth lenses are made of a plastic material.Type: ApplicationFiled: April 1, 2019Publication date: April 2, 2020Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Kyu Min CHAE, Eun Chong LEE
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Publication number: 20200083591Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.Type: ApplicationFiled: August 19, 2019Publication date: March 12, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Sheng-Chi HSIEH, Chen-Chao WANG, Teck-Chong LEE, Chien-Hua CHEN
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Publication number: 20200075571Abstract: A semiconductor device package includes a carrier, an electronic component, a protection layer, a conductive layer and an integrated passive device (IPD). The electronic component is disposed on the carrier. The protection layer covers the carrier and the electronic component. The conductive layer is disposed on the protection layer and penetrates the protection layer to be electrically connected to the electronic component. The IPD is disposed on the conductive layer and electrically connected to the electronic component through the conductive layer.Type: ApplicationFiled: September 4, 2019Publication date: March 5, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Hua CHEN, Teck-Chong LEE
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Publication number: 20190393297Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.Type: ApplicationFiled: June 20, 2019Publication date: December 26, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Chien-Hua CHEN, Teck-Chong LEE, Hung-Yi LIN, Pao-Nan LEE, Hsin Hsiang WANG, Min-Tzu HSU, Po-Hao CHEN
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Publication number: 20190369365Abstract: An optical imaging system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens sequentially disposed in numerical order along an optical axis of the optical imaging system from an object side of the optical imaging system toward an imaging plane of the optical imaging system, wherein the first to seventh lenses are spaced apart from each other along the optical axis, and the optical imaging system satisfies 0.4<L1TR/L7TR<1.9, where L1TR is an overall outer diameter of the first lens, L7TR is an overall outer diameter of the seventh lens, and L1TR and L7TR are expressed in a same unit of measurement.Type: ApplicationFiled: May 28, 2019Publication date: December 5, 2019Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Hag Chul KIM, Eun Chong LEE, Yong Joo JO, Ga Young AN
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Patent number: 10490341Abstract: An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.Type: GrantFiled: August 17, 2017Date of Patent: November 26, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Teck-Chong Lee, Sheng-Chi Hsieh, Chien-Hua Chen
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Patent number: 10475718Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.Type: GrantFiled: May 18, 2017Date of Patent: November 12, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Hua Chen, Hung-Yi Lin, Cheng-Yuan Kung, Teck-Chong Lee, Shiuan-Yu Lin
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Publication number: 20190230944Abstract: Seafood products are made from squid by cleaning a squid by removing arms and tentacles from the squid; removing visceral content from the squid; steam cooking the squid; reducing the moisture content of the squid to between 40% by weight and 72% by weight; and shredding the squid after the step of reducing the moisture content. The shredded squid can be treated with marinades for flavor enhancement to create a variety of world cuisine tastes. The product is ready to serve without further cooking.Type: ApplicationFiled: September 11, 2017Publication date: August 1, 2019Inventors: Neal NAITO, Chong LEE
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Patent number: 10251315Abstract: One feature pertains to cooling of a high density array of non-volatile memory mass storage devices within a computer enclosure. A coolant is moved through the enclosure through two separate air paths, each serving approximately half of the mass storage devices. The two air paths are interleaved in a central duct ported to a frontal and a rear plenum. The central duct contains two groups of fans with a flow axis perpendicular to the plane of the server enclosure but with opposite flow direction with the two groups vertically offset relative to each other. The two paths are separated from each other through dividers. Both paths intake coolant from the cold isle and exhaust the coolant to the hot isle. The non-volatile memory mass storage devices include electromechanical and solid state devices.Type: GrantFiled: April 20, 2018Date of Patent: April 2, 2019Assignee: SANMINA CORPORATIONInventors: Matthew Phillip Mitchell, Eugene McCabe, Ritesh Kumar, Donald Chong Lee, Franz Michael Schuette
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Publication number: 20190074908Abstract: A coherent optical receiver having an analog electrical circuit connected to combine the outputs of multiple photodetectors to generate an electrical output signal from which the data encoded in a received modulated optical signal can be recovered in a robust and straightforward manner. In an example embodiment, the analog electrical circuit includes one or more transimpedance amplifiers connected between the photodetectors and the receiver's output port. The coherent optical receiver may include a dual-polarization optical hybrid coupled to eight photodiodes to enable polarization-insensitive detection of the received modulated optical signal. The signal processing implemented in the analog electrical circuit advantageously enables the use of relatively inexpensive local-oscillator sources that may have relaxed specifications with respect to linewidth and wavelength stability.Type: ApplicationFiled: September 6, 2017Publication date: March 7, 2019Applicant: Nokia Solutions and Networks OYInventors: Sian Chong Lee, Vincent Houtsma, Doutje van Veen, Chen Zhu, Noriaki Kaneda, Michael Eggleston
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Publication number: 20190067261Abstract: An integrated passive component comprises a capacitor, a first passivation layer, an inductor, an insulation layer and an external contact. The first passivation layer surrounds the capacitor. The inductor is on the first passivation layer and electrically connected to the capacitor. The inductor comprises a plurality of conductive pillars. The insulation layer is on the first passivation layer and surrounds each of the conductive pillars. The insulation layer comprises a first surface adjacent to the first passivation layer, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface. A ratio of a width of each of the conductive pillars to a height of each of the conductive pillars is about 1:7. The external contact is electrically connected to the inductor and contacts the second surface of the insulation layer and the side surface of the insulation layer.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Shun CHANG, Teck-Chong LEE, Chien-Hua CHEN
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Publication number: 20190057809Abstract: An electrical device comprises a substrate, a first dielectric layer, a first die, an adjustable inductor and a second die. The substrate has a first surface. The first dielectric layer is disposed on the first surface of the substrate and has a first surface. The first die is surrounded by the first dielectric layer. The adjustable inductor is electrically connected to the first die. The adjustable inductor comprises a plurality of pillars surrounded by the first dielectric layer, a plurality of first metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars, and a plurality of second metal strips disposed on the first surface of the first dielectric layer and electrically connected to the pillars. A width of at least one of the second metal strips is different than a width of at least one of the first metal strips. The second die is electrically connected to the adjustable inductor.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Teck-Chong LEE, Sheng-Chi HSIEH, Chien-Hua CHEN
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METHOD, APPARATUS, AND SYSTEM FOR POWER MANAGEMENT ON A CPU DIE VIA CLOCK REQUEST MESSAGING PROTOCOL
Publication number: 20190041936Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.Type: ApplicationFiled: January 12, 2018Publication date: February 7, 2019Inventors: Poh Thiam Teoh, Mikal C. Hunsaker, Su Wei Lim, Gim Chong Lee, Hooi Kar Loo, Shashitheren Kerisnan, Siang Lin Tan, Ming Chew Lee, Ngeok Kuan Wai, Li Len Lim