Abstract: A display panel with secured mechanical reliability comprises: a first plate including a display region and a non display region, a second plate facing the first plate, a first frit portion interposed between the first plate and the second plate and sealing the display region from outside, and a second frit portion separated from the first fit portion and comprising a plurality of sub-frits isolated from each other. The sub-frits are located between a first line which passes through points closest to edges of the first plate among outer points of the first frit portion with respect to a sealed space and extends parallel to the edges of the first plate and a second line which passes through points furthest from the edges of the first plate among inner points of the first frit portion with respect to the sealed space and extends parallel to the edges of the first plate.

Abstract: Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

Abstract: An anisotropic conductive film (ACF) is disclosed. The ACF includes a film, an adhesive layer positioned on the film, and one or more conductive balls within the adhesive layer. The conductive balls include a first core part having a first hardness, a second core part covering the first core part and having a second hardness that is greater than the first hardness, and a conductive part covering the second core part, respectively.

Abstract: A display apparatus having an improved function for encapsulating a display unit, and comprising a substrate, wherein the display unit is disposed on the substrate; an encapsulation unit facing the display unit, the encapsulation unit comprising: a metal layer; and a composite member; and a sealing unit disposed between the substrate and the encapsulation unit and separated from the display unit so as to adhere the substrate to the encapsulation unit, wherein the composite member comprises a resin matrix and carbon fibers, and wherein the metal layer is disposed between the substrate and the composite member.

Abstract: A display apparatus including: a display unit disposed on a substrate; an encapsulation unit facing the display unit, the encapsulation unit including: a metal layer; a complex member; and a reinforcement member formed on an upper surface of the complex member; and a sealing unit disposed between the substrate and the encapsulation unit and apart from the display unit to bond the substrate and the encapsulation unit to the sealing unit.

Abstract: A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches.

Abstract: A resin fluid dispensing apparatus includes a container having a first volume arranged to receive a resin fluid, a first connection unit connected to the container, a pressure chamber having a second volume configured to connect to the first connection unit and to contain the resin fluid transported from the first volume through the first connection unit, a pressure unit including a pressure plate directly pressurizing the resin fluid in the second volume, a dispenser having a syringe arranged to receive the pressurized resin fluid transported from the second volume through a second connection unit connected to the pressure chamber and to dispense the received pressurized resin fluid through the syringe.

Abstract: A display device includes a wire substrate including a wire unit for driving the display device, an integrated circuit chip mounted at the wire substrate, and a pad unit extended from the wire unit to be disposed between the wire substrate and the integrated circuit chip. The pad unit is connected to the integrated circuit chip. The pad unit includes a first conductive layer extended from the wire unit, and a second conductive layer disposed on the first conductive layer. The hardness of the second conductive layer is less than the hardness of the first conductive layer.

Abstract: A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

Abstract: Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region.

Abstract: Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

Abstract: A display panel with secured mechanical reliability comprises: a first plate including a display region having light emitters and a non-display region, a second plate facing the first plate, a first frit portion interposed between the first plate and the second plate and sealing the display region from the outside, and a second frit portion separated from the first frit portion and comprising a plurality of sub-frits isolated from each other, wherein the sub-frits are located between a first line which passes through points closest to edges of the first plate among outer points of the first frit portion with respect to a sealed space and extends parallel to the edges of the first plate and a second line which passes through points furthest from the edges of the first plate among inner points of the first frit portion with respect to the sealed space and extends parallel to the edges of the first plate.

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.

Abstract: Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings.

Abstract: A large size organic light emitting diode (OLED) display and manufacturing method thereof are disclosed. In one embodiment, the method includes i) forming a display unit including a plurality of pixels on a substrate, ii) forming a getter layer, a bonding layer and a conductive contact layer around the display unit and iii) manufacturing a sealing member including a flexible polymer film and a metal layer formed on at least one side of the polymer film. The method may further include laminating the sealing member on the substrate using a roll lamination process such that the metal layer contacts the conductive contact layer and curing the contact layer and the conductive contact layer.

Abstract: Disclosed is a substrate for a display device that includes a composite material layer including an inorganic fiber material and a resin, and a metal layer disposed on the composite material layer, and a display device including the substrate.