Abstract: Disclosed is an image sensing device including a pixel array including a plurality of pixels arranged in rows and columns, and suitable for outputting a plurality of pixel signals, and a plurality of readout circuits coupled to the pixel array, and suitable for compensating for readout deviations among the plurality of pixel signals, based on a plurality of bias voltages having different voltage levels, when reading out the plurality of pixel signals.

Abstract: An image sensing device includes a pixel array including a plurality of pixels arranged in rows and columns, and suitable for outputting a plurality of pixel signals, and a plurality of readout circuits coupled to the pixel array, and suitable for compensating for readout deviations among the plurality of pixel signals when reading out the plurality of pixel signals.

Abstract: Disclosed is an image sensing device including a pixel array including a plurality of pixels arranged in rows and columns, and suitable for outputting a plurality of pixel signals, and a plurality of readout circuits coupled to the pixel array, and suitable for compensating for readout deviations among the plurality of pixel signals, based on a plurality of bias voltages having different voltage levels, when reading out the plurality of pixel signals.

Abstract: An image sensing device includes a pixel array including a plurality of pixels arranged in rows and columns, and suitable for outputting a plurality of pixel signals, and a plurality of readout circuits coupled to the pixel array, and suitable for compensating for readout deviations among the plurality of pixel signals when reading out the plurality of pixel signals.

Abstract: A source driver includes a latch configured to store data based on or in response to a latch signal and output the data stored in the latch, a resistor string including a plurality of resistors configured to provide a plurality of grayscale voltages, a decoder connected to the resistor string, configured to select and output one of the plurality of grayscale voltages based on or in response to the data from the latch, an amplifier including a first input terminal, a second input terminal and an output terminal, a first control switch between the decoder and the first input terminal of the amplifier, and a second control switch between the first input terminal and the second input terminal of the amplifier. The first control switch and the second control switch are alternately turned on and off.

Abstract: A source driver includes a latch configured to store data based on or in response to a latch signal and output the data stored in the latch, a resistor string including a plurality of resistors configured to provide a plurality of grayscale voltages, a decoder connected to the resistor string, configured to select and output one of the plurality of grayscale voltages based on or in response to the data from the latch, an amplifier including a first input terminal, a second input terminal and an output terminal, a first control switch between the decoder and the first input terminal of the amplifier, and a second control switch between the first input terminal and the second input terminal of the amplifier. The first control switch and the second control switch are alternately turned on and off.

Abstract: A gate driver is disclosed. The disclosed gate driver includes a shift register configured to generate a shift signal. The shift signal is based on a gate start signal and a gate clock signal. The gate driver further includes a gate drive signal generator configured to generate a gate drive signal. The gate drive signal is based on a gate control signal and the shift signal. The rising edge of the gate control signal precedes the falling edge of the shift signal, and the falling edge of the gate control signal follows the falling edge of the shift signal. The gate drive signal falls from a second voltage to a third voltage in response to the falling edge of the shift signal and rises from the third voltage to a first voltage in response to the falling edge of the gate control signal. The first voltage is higher than the third voltage but lower than the second voltage.

Abstract: A data driver includes a data storage unit configured to store a data signal therein, a level shifting block configured to shift a level of the data signal and output a level shifted data signal based on the result of the level shifting, a waveform conversion block configured to convert a waveform of the level shifted data signal and generate a conversion data signal (e.g., based on the waveform conversion), and a digital-analog conversion unit configured to output an analog signal based on the conversion data signal, wherein the conversion data signal has a rising time and a descending time that are different from each other.

Abstract: A data driver includes a data storage unit configured to store a data signal therein, a level shifting block configured to shift a level of the data signal and output a level shifted data signal based on the result of the level shifting, a waveform conversion block configured to convert a waveform of the level shifted data signal and generate a conversion data signal (e.g., based on the waveform conversion), and a digital-analog conversion unit configured to output an analog signal based on the conversion data signal, wherein the conversion data signal has a rising time and a descending time that are different from each other.

Abstract: A data driver includes a random delay unit configured to receive and delay a first control signal and to generate a random delay signal based on the delay, a latch unit configured to store data in response to the random delay signal, a digital-analog conversion unit configured to convert the data from the latch unit into an analog signal, and an output unit configured to amplify and output the analog signal, wherein the time delay between the first control signal and the random delay signal is random.

Abstract: A gate driver is disclosed. The disclosed gate driver includes a shift register configured to generate a shift signal. The shift signal is based on a gate start signal and a gate clock signal. The gate driver further includes a gate drive signal generator configured to generate a gate drive signal. The gate drive signal is based on a gate control signal and the shift signal. The rising edge of the gate control signal precedes the falling edge of the shift signal, and the falling edge of the gate control signal follows the falling edge of the shift signal. The gate drive signal falls from a second voltage to a third voltage in response to the falling edge of the shift signal and rises from the third voltage to a first voltage in response to the falling edge of the gate control signal. The first voltage is higher than the third voltage but lower than the second voltage.

Abstract: A circuit and method for driving a line repair amplifier includes a line repair amplifier which can be driven by using a single side input which can use an amplifier which drives a gray high side only and an amplifier which drives a gray low side only separately in a liquid crystal display device which uses a line repair amplifier.

Abstract: A circuit and method for driving a line repair amplifier includes a line repair amplifier which can be driven by using a single side input which can use an amplifier which drives a gray high side only and an amplifier which drives a gray low side only separately in a liquid crystal display device which uses a line repair amplifier.