Abstract: In some aspects, the disclosure is directed to methods and systems for utilizing a thin-film bulk acoustic resonator (FBAR) as a frequency reference for a phase-locked loop (PLL) circuit controlling frequency of a voltage controlled oscillator (VCO). In some implementations, the FBAR-based oscillator may be used as a reference to an analog or digital PLL circuit (either directly, or divided to a lower frequency). In other implementations, the FBAR-based oscillator may be used as a reference to a mixing-based PLL rather than a dividing-based PLL. Through these implementations, the noise contribution of many of the PLL circuit components or elements may be reduced (e.g. noise from a delta-sigma modulator (DSM), multiple modulus divider (MMD), phase frequency detector (PFD)/charge pump (CP), etc.).

Abstract: A synchronous switching regulator circuit for supply regulation of a switching circuit includes a pass transistor to couple the switching circuit to a supply voltage. The synchronous switching regulator circuit further includes a switch that is operable to synchronously turn off a flow of a supply current through the pass transistor. The switching circuit can be controlled by a switching signal, and the switch can operate in synchronization with the switching circuit.

Abstract: A synchronous switching regulator circuit for supply regulation of a switching circuit includes a pass transistor to couple the switching circuit to a supply voltage. The synchronous switching regulator circuit further includes a switch that is operable to synchronously turn off a flow of a supply current through the pass transistor. The switching circuit can be controlled by a switching signal, and the switch can operate in synchronization with the switching circuit.

Abstract: A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

Abstract: A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

Abstract: An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex modulated MSK signal with only a single path receiver chain. According to an embodiment of the present invention, the overall power consumption of the radio receiver in the present invention can be reduced by almost fifty percent compared to that of the conventional complex path radio receiver architecture. The radio receiver architecture of the invention is suitable for the ultra low power radio application such as wireless sensor networks (WSN).

Abstract: An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex modulated MSK signal with only a single path receiver chain. According to an embodiment of the present invention, the overall power consumption of the radio receiver in the present invention can be reduced by almost fifty percent compared to that of the conventional complex path radio receiver architecture. The radio receiver architecture of the invention is suitable for the ultra low power radio application such as wireless sensor networks (WSN).

Abstract: A radio frequency (RF) filter is provided which includes a band pass filter unit and an amplifying unit. If a signal having a frequency in a first band is input, the RF filter performs band pass filtering, and if a signal having a frequency in a second band is input, the RF filter performs an amplifying process. The RF filter can be used for various RF signal processing devices, such as digital broadcast receiving tuners.

Abstract: A digitally controlled oscillator (DCO) includes a current generator which generates an electric current having a magnitude corresponding to an input signal, and a digitally controlled oscillating unit which generates an oscillating frequency based on an inductance which varies according to the magnitude of the electric current generated by the current generator.

Abstract: A low noise amplifier (LNA) for ultra wide band receives and amplifies identical RF signals in different frequency bands, and includes more than one pair of narrow band LNAs coupled in parallel, and a load circuit which increases load impedance of the entire circuit of the narrow band LNAs. The LNA can not only amplify the RF signal in the UWB but also obtain the low noise and the high gain that are features of the conventional narrow band LNA.

Abstract: A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

Abstract: A fast mode switching frequency synthesizing apparatus and method for operating in low power consumption. In the frequency synthesizer, according to a mode control signal, an SSB mixer selectively generates and outputs a signal having a frequency which is identical to an input signal RF or outputs a signal having a frequency which is a synthesized frequency of the input signals RF and LO. Frequency synthesized signals having a frequency which is a sum of frequencies of the input signals RF and LO, or a difference of frequencies therebetween, may be generated by changing wiring of a path switch according to a phase control signal.

Abstract: A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.

Abstract: A low noise amplifier (LNA) for ultra wide band receives and amplifies identical RF signals in different frequency bands, and includes more than one pair of narrow band LNAs coupled in parallel, and a load circuit which increases load impedance of the entire circuit of the narrow band LNAs. The LNA can not only amplify the RF signal in the UWB but also obtain the low noise and the high gain that are features of the conventional narrow band LNA.

Abstract: A multi-input multi-frequency synthesizing apparatus and method for a multi-band radio frequency (RF) receiver. The frequency synthesizing apparatus may generate an output from a greater number of high frequency signals by using one multi-input single side band (SSB) mixer. The multi-input SSB mixer may generate a signal whose frequency is an addition of frequencies of two signals selected from a signal selection control unit, or a difference of frequencies therebetween. According to a circuit configuration of the multi-input SSB mixer, the signal selection control unit may select more than two signals.

Abstract: An adjustable inductor includes a first conductor line to receive an alternating current (AC) signal, a second conductor line configured in a loop arrangement, to generate an inducting current upon receiving the AC signal at the first conductor line, and a switch to adjust an inductance of the first conductor line by switching a loop connection of the second conductor line according to an external control signal.

Abstract: A digitally controlled oscillator (DCO) includes a current generator which generates an electric current having a magnitude corresponding to an input signal, and a digitally controlled oscillating unit which generates an oscillating frequency based on an inductance which varies according to the magnitude of the electric current generated by the current generator.

Abstract: A low noise amplifier (LNA) for ultra wide band receives and amplifies identical RF signals in different frequency bands, and includes more than one pair of narrow band LNAs coupled in parallel, and a load circuit which increases load impedance of the entire circuit of the narrow band LNAs. The LNA can not only amplify the RF signal in the UWB but also obtain the low noise and the high gain that are features of the conventional narrow band LNA.

Abstract: A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.

Abstract: A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.