Patents by Inventor Choong Bin Yim
Choong Bin Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240128173Abstract: A semiconductor package includes a first package substrate having a first region and a second region, which do not overlap each other, a first connection element having a first height on the first region, a first semiconductor chip having a second height connected to the first connection element, a second connection element having a third height on the second region, a third connection element having a fourth height on the second connection element and electrically connected to the second connection element, a second package on the third connection element, the second package including a second package substrate and a second semiconductor chip, and a first mold layer covering at least a portion of the first semiconductor chip, covering at least a portion of the second connection element, covering the first package substrate, exposing upper surfaces of the first semiconductor chip and the second connection element, and having a fifth height.Type: ApplicationFiled: May 19, 2023Publication date: April 18, 2024Inventors: Ji-Yong Park, Jong Bo Shim, Dae Hun Lee, Choong Bin Yim
-
Publication number: 20240105567Abstract: A semiconductor package includes a first package substrate having a first area and a second area that is distinct and separate from the first area, a first connection element disposed on the first area and having a first thickness, a first semiconductor chip connected to the first connection element, a second connection element disposed on the second area and having a second thickness that is greater than the first thickness, a third connection element disposed on the second connection element and electrically connected to the second connection element, a second package substrate disposed on the third connection element, and a second semiconductor chip disposed on the second package substrate.Type: ApplicationFiled: August 23, 2023Publication date: March 28, 2024Inventors: Choong Bin YIM, Ji Yong PARK, Jong Bo SHIM
-
Publication number: 20240055398Abstract: A semiconductor package includes a first substrate, a memory semiconductor package on a first surface of the first substrate, an adhesive layer between the first surface of the first substrate and the memory semiconductor package, a wire extending from an upper surface of the memory semiconductor package and connected to the first substrate, a logic semiconductor chip on the first surface of the first substrate, a first connection terminal between the first surface of the first substrate and the logic semiconductor chip, and a molding layer, wherein a first height of the memory semiconductor package is smaller than a second height of the logic semiconductor chip, and wherein an uppermost surface of the molding layer and the upper surface of the logic semiconductor chip are coplanar.Type: ApplicationFiled: April 28, 2023Publication date: February 15, 2024Inventors: Choong Bin Yim, Ji-Yong Park, Jin-Woo Park, Jong Bo Shim
-
Publication number: 20230111343Abstract: A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.Type: ApplicationFiled: October 7, 2022Publication date: April 13, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Choong Bin YIM, Ji Hwang KIM, Jin-woo PARK, Jong Bo SHIM
-
Patent number: 9245863Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.Type: GrantFiled: July 16, 2013Date of Patent: January 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-jung Yu, Hak-kyoon Byun, Kyung-tae Na, Seung-hun Han, Tae-sung Park, Choong-bin Yim
-
Patent number: 9190401Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: GrantFiled: May 23, 2014Date of Patent: November 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Bin Yim, Seung-Kon Mok, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim
-
Patent number: 8952513Abstract: A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.Type: GrantFiled: October 24, 2011Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-bin Yim, Dae-Young Choi, Mi-Yeon Kim, Ji-yong Park
-
Publication number: 20140256089Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Choong-Bin YIM, Seung-Kon MOK, Jin-Woo PARK, Dae-Young CHOI, Mi-Yeon KIM
-
Patent number: 8759959Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: GrantFiled: February 17, 2011Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Bin Yim, Seung-Kon Mok, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim
-
Publication number: 20140091463Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.Type: ApplicationFiled: July 16, 2013Publication date: April 3, 2014Inventors: Hae-jung YU, Hak-kyoon BYUN, Kyung-tae NA, Seung-hun HAN, Tae-sung PARK, Choong-bin YIM
-
Patent number: 8530280Abstract: A method for manufacturing an integrated circuit package system includes: providing a carrier; mounting an integrated circuit die on a top side of the carrier; connecting the integrated circuit die with the carrier; forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress; and forming a first external interconnect on the top side of the carrier adjacent to and separated from the encapsulation including forming a second external interconnect on a bottom side of the carrier opposite the first external interconnect.Type: GrantFiled: July 7, 2011Date of Patent: September 10, 2013Assignee: Stats Chippac Ltd.Inventors: Choong Bin Yim, Young Cheol Kim
-
Patent number: 8367465Abstract: A integrated circuit package on package system is provided including providing a base substrate having a base stackable connection, attaching a base integrated circuit on the base substrate, forming a stackable package including the base integrated circuit encapsulated with the base stackable connection partially exposed, and attaching a bottom package on the stackable package.Type: GrantFiled: March 17, 2006Date of Patent: February 5, 2013Assignee: STATS Chippac Ltd.Inventors: DongSam Park, Choong Bin Yim, In Sang Yoon
-
Publication number: 20120168917Abstract: A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.Type: ApplicationFiled: October 24, 2011Publication date: July 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choong-bin YIM, Dae-Young CHOI, Mi-Yeon KIM, Ji-yong PARK
-
Patent number: 8187921Abstract: A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension.Type: GrantFiled: July 14, 2011Date of Patent: May 29, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-bin Yim, Tae-je Cho
-
Publication number: 20110275177Abstract: A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension.Type: ApplicationFiled: July 14, 2011Publication date: November 10, 2011Inventors: Choong-bin Yim, Tae-je Cho
-
Patent number: 8049322Abstract: A method for making an integrated circuit package-in-package system includes: forming a first integrated circuit package including a first device and a first substrate and having a first interface; stacking a second integrated circuit package including a second device and a second substrate and having a second interface above the first integrated circuit package; and fitting the first interface directly on the second interface.Type: GrantFiled: April 30, 2010Date of Patent: November 1, 2011Assignee: Stats Chippac Ltd.Inventors: Choong Bin Yim, Hyeog Chan Kwon, Jong-Woo Ha
-
Publication number: 20110260313Abstract: A method for manufacturing an integrated circuit package system includes: providing a carrier; mounting an integrated circuit die on a top side of the carrier; connecting the integrated circuit die with the carrier; forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress; and forming a first external interconnect on the top side of the carrier adjacent to and separated from the encapsulation including forming a second external interconnect on a bottom side of the carrier opposite the first external interconnect.Type: ApplicationFiled: July 7, 2011Publication date: October 27, 2011Inventors: Choong Bin Yim, Young Cheol Kim
-
Publication number: 20110215451Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.Type: ApplicationFiled: February 17, 2011Publication date: September 8, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choong-Bin Yim, Seung-Kon Mok, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim
-
Patent number: 7999368Abstract: A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension.Type: GrantFiled: August 26, 2009Date of Patent: August 16, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-bin Yim, Tae-je Cho
-
Patent number: 7985623Abstract: An integrated circuit package system is provided including providing a carrier, mounting an integrated circuit die on the carrier, connecting the integrated circuit die with the carrier, and forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress.Type: GrantFiled: April 13, 2007Date of Patent: July 26, 2011Assignee: Stats Chippac Ltd.Inventors: Choong Bin Yim, Young Cheol Kim