Abstract: A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

Abstract: A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

Abstract: A method of manufacturing a non-volatile memory device and a non-volatile memory device are provided. The method includes: providing a substrate on which a plurality of charge storage layers that are electrically separated from each other by device isolation layers are formed; recessing the device isolation layers such that an uppermost portion of the device isolation layers is lower than an uppermost portion of the charge storage layers; and dry cleaning first and second sides of each of the charge storage layers that are exposed by the device isolation layers by using a cleaning agent including NF3 gas.

Abstract: A slurry composition for a chemical mechanical polishing process and a method of manufacturing a semiconductor memory device using the slurry composition are provided. The slurry composition may include about 0.001 percent by weight to about 5 percent by weight of a ceria abrasive, about 0.001 percent by weight to about 0.1 percent by weight of a nonionic surfactant adsorbed onto a polysilicon layer forming a passivation layer on the polysilicon layer, the nonionic surfactant having a chemical structure of a triblock copolymer including a first polyethylene oxide block, a polypropylene oxide block and a second polyethylene oxide block and a remainder of water.

Abstract: A slurry composition for a chemical mechanical polishing process and a method of manufacturing a semiconductor memory device using the slurry composition are provided. The slurry composition may include about 0.001 percent by weight to about 5 percent by weight of a ceria abrasive, about 0.001 percent by weight to about 0.1 percent by weight of a nonionic surfactant adsorbed onto a polysilicon layer forming a passivation layer on the polysilicon layer, the nonionic surfactant having a chemical structure of a triblock copolymer including a first polyethylene oxide block, a polypropylene oxide block and a second polyethylene oxide block and a remainder of water.

Abstract: Provided is a method of fabricating an integrated circuit semiconductor device. The method may include forming a plurality of gate patterns spaced apart from each other on a semiconductor substrate, the plurality of gate patterns including gate electrodes and gate capping patterns. After an interlayer insulating layer is formed to insulate the gate patterns, the interlayer insulating layer and the gate capping patterns may be planarized by etching until top surfaces of the gate electrodes are exposed. Gate metal silicide layers may be selectively formed on the gate electrodes.

Abstract: A slurry composition for a chemical mechanical polishing process and a method of manufacturing a semiconductor memory device using the slurry composition are provided. The slurry composition may include about 0.001 percent by weight to about 5 percent by weight of a ceria abrasive, about 0.001 percent by weight to about 0.1 percent by weight of a nonionic surfactant adsorbed onto a polysilicon layer forming a passivation layer on the polysilicon layer, the nonionic surfactant having a chemical structure of a triblock copolymer including a first polyethylene oxide block, a polypropylene oxide block and a second polyethylene oxide block and a remainder of water.

Abstract: A slurry delivery system, a chemical mechanical polishing (CMP) apparatus, and method for using the same are provided. An apparatus for supplying slurry to a polishing unit may include a first feed line through which an abrasive may be supplied at a first velocity. A velocity-changing member may be connected to the first feed line, and/or a velocity of the abrasive may be changed from the first velocity to. the second velocity different from the first velocity by the velocity-changing member. A second feed line may be connected to the velocity-changing member and/or an additive may be supplied through the second feed line. A supply line may be connected to the velocity-changing member. A slurry, which may be a mixture of the abrasive and/or the additive, may be supplied to a polishing unit through the supply line. Accordingly, the slurry may be more uniformly mixed and/or supplied to a polishing unit.

Abstract: A slurry delivery system, a chemical mechanical polishing (CMP) apparatus, and method for using the same are provided. An apparatus for supplying slurry to a polishing unit may include a first feed line through which an abrasive may be supplied at a first velocity. A velocity-changing member may be connected to the first feed line, and/or a velocity of the abrasive may be changed from the first velocity to. the second velocity different from the first velocity by the velocity-changing member. A second feed line may be connected to the velocity-changing member and/or an additive may be supplied through the second feed line. A supply line may be connected to the velocity-changing member. A slurry, which may be a mixture of the abrasive and/or the additive, may be supplied to a polishing unit through the supply line. Accordingly, the slurry may be more uniformly mixed and/or supplied to a polishing unit.