Patents by Inventor Chorng-Ping Chang
Chorng-Ping Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9023723Abstract: A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less.Type: GrantFiled: May 9, 2013Date of Patent: May 5, 2015Assignee: Applied Materials, Inc.Inventors: Chorng-Ping Chang, Er-Xuan Ping, Judon Tony Pan
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Patent number: 8895432Abstract: A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less.Type: GrantFiled: May 8, 2013Date of Patent: November 25, 2014Assignee: Applied Materials, Inc.Inventors: Chorng-Ping Chang, Bingxi Wood, Er-Xuan Ping
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Publication number: 20130320542Abstract: A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less.Type: ApplicationFiled: May 8, 2013Publication date: December 5, 2013Inventors: Chorng-Ping Chang, Bingxi Wood, Er-Xuan Ping
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Publication number: 20130323920Abstract: A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less.Type: ApplicationFiled: May 9, 2013Publication date: December 5, 2013Inventors: Chorng-Ping Chang, Er-Xuan Ping, Judon Tony Pan
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Patent number: 8293460Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.Type: GrantFiled: December 19, 2008Date of Patent: October 23, 2012Assignee: Applied Materials, Inc.Inventors: Hui W. Chen, Chorng-Ping Chang, Yongmei Chen, Huixiong Dai, Jiahua Yu, Susie X. Yang, Xumou Xu, Christopher D. Bencher, Raymond Hoiman Hung, Michael P. Duane, Christopher Siu Wing Ngai, Jen Shu, Kenneth MacWilliams
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Patent number: 7892911Abstract: Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of the trench and above the substrate. A gate electrode has a work-function-setting layer disposed along the sidewalls of the trench and above the gate dielectric layer at the bottom of the trench. The work-function-setting layer has a thickness at the bottom of the trench greater than the thickness along the sidewalls of the trench. A pair of source and drain regions is disposed in the substrate, on either side of the gate electrode.Type: GrantFiled: January 10, 2008Date of Patent: February 22, 2011Assignee: Applied Materials, Inc.Inventors: Bingxi Sun Wood, Chorng-Ping Chang
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Publication number: 20090311635Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.Type: ApplicationFiled: December 19, 2008Publication date: December 17, 2009Inventors: HUI W. CHEN, CHORNG-PING CHANG, YONGMEI CHEN, HUIXIONG DAI, JIAHUA YU, SUSIE X. YANG, XUMOU XU, CHRISTOPHER D. BENCHER, RAYMOND HOIMAN HUNG, MICHAEL P. DUANE, CHRISTOPHER SIU WING NGAI, JEN SHU, KENNETH MACWILLIAMS
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Publication number: 20090189201Abstract: Inward dielectric spacers for a replacement gate integration scheme are described. A semiconductor device is fabricated by first providing a substrate having thereon a placeholder gate electrode disposed in a dielectric layer. The placeholder gate electrode is removed to from a trench in the dielectric layer. A pair of dielectric spacers is then formed adjacent to the sidewalls of the trench. Finally, a gate electrode is formed in the trench and adjacent to the pair of dielectric layers.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Inventors: Chorng-Ping Chang, Bingxi Sun Wood
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Publication number: 20090179285Abstract: Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of the trench and above the substrate. A gate electrode has a work-function-setting layer disposed along the sidewalls of the trench and above the gate dielectric layer at the bottom of the trench. The work-function-setting layer has a thickness at the bottom of the trench greater than the thickness along the sidewalls of the trench. A pair of source and drain regions is disposed in the substrate, on either side of the gate electrode.Type: ApplicationFiled: January 10, 2008Publication date: July 16, 2009Inventors: Bingxi Sun Wood, Chorng-Ping Chang
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Patent number: 7547621Abstract: A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.Type: GrantFiled: July 25, 2006Date of Patent: June 16, 2009Assignee: Applied Materials, Inc.Inventors: Rajesh Kanuri, Chorng-Ping Chang, Christopher Dennis Bencher, Hoiman Hung
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Publication number: 20080026584Abstract: A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.Type: ApplicationFiled: July 25, 2006Publication date: January 31, 2008Inventors: Rajesh Kanuri, Chorng-Ping Chang, Christopher Dennis Bencher, Hoiman Hung
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Publication number: 20040137688Abstract: A semiconductor device, and a process for fabricating the device, is disclosed. The semiconductor device is an MOS device in which the gate is bounded by spacers, which are in turn bounded by a trench in a trench dielectric layer formed on a semiconductor substrate. The device is formed by lithographically defining a sacrificial gate on the surface of the semiconductor substrate. The trench dielectric layer is then formed on the semiconductor substrate and adjacent to the sacrificial gate. The trench dielectric layer is planarized and, subsequent to planarization, the sacrificial gate is no longer covered by the trench dielectric layer. The sacrificial gate is then removed, which leaves a trench in the trench dielectric layer. Dielectric spacers are then formed in the trench. The distance between the spacers defines the gate length of the semiconductor device. After the spacers are formed, the device gate is formed. At least a portion of the gate is formed in the trench.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Inventors: Chorng-Ping Chang, Chien-Shing Pai, Thi-Hong-Ha Vuong
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Patent number: 6566224Abstract: The invention is a process for device fabrication that utilizes shallow trench isolation. The process involves the steps of forming an oxidation barrier region, e.g., silicon nitride, above a silicon substrate, providing an opening in the oxidation barrier region and in any underlying regions deposited on the silicon, providing a trench in the silicon substrate at the opening, depositing a dielectric material such as silicon dioxide in the trench, typically planarizing the trench silicon dioxide, and subsequently performing an oxidation step. The oxidation step rounds the otherwise sharp corners of the silicon at the area where the trench silicon dioxide meets the pad oxide. The invention thereby reduces or eliminates sharp corners that contribute to leakage current.Type: GrantFiled: July 31, 1997Date of Patent: May 20, 2003Assignee: Agere Systems, Inc.Inventors: Chorng-Ping Chang, Chien-Shing Pai
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Patent number: 6469390Abstract: It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.Type: GrantFiled: April 21, 1999Date of Patent: October 22, 2002Assignee: Agere Systems Guardian Corp.Inventors: Chorng-Ping Chang, Kin Ping Cheung, Chien-Shing Pai, Wei Zhu
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Publication number: 20020000669Abstract: It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.Type: ApplicationFiled: April 21, 1999Publication date: January 3, 2002Inventors: CHORNG-PING CHANG, KIN PING CHEUNG, CHIEN-SHING PAI, WEI ZHU
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Patent number: 5438006Abstract: An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.Type: GrantFiled: January 3, 1994Date of Patent: August 1, 1995Assignee: AT&T Corp.Inventors: Chorng-Ping Chang, Kuo-Hua Lee, Chun-Ting Liu, Ruichen Liu
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Patent number: 4960656Abstract: Silicon nitride regions suitable for applications such as capping layers in integrated circuit fabrication are produced by an advantageous plasma deposition process. This process utilizes a combination of gases, including a silicon-containing gas, a nitrogen-containing gas, a fluorine-containing gas, and a hydrogen-containing gas. Silicon nitride having a low density of defect states and thus having excellent dielectric properties is produced.Type: GrantFiled: December 12, 1989Date of Patent: October 2, 1990Assignee: AT&T Bell LaboratoriesInventors: Chorng-Ping Chang, Daniel L. Flamm, Dale E. Ibbotson, John A. Mucha