Patents by Inventor Chou Lin

Chou Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240338507
    Abstract: The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 10, 2024
    Inventors: Jen-Yuan CHANG, Jheng-Hong JIANG, Chin-Chou LIU, Long Song LIN
  • Publication number: 20240341030
    Abstract: A printed circuit board structure includes a plurality of interface layers; and a detection window, arranged in a plurality of detection regions corresponding to a projected position of a detection entrance in the plurality of interface layers, wherein the detection window is utilized for detecting a plurality of characteristics of the plurality of interface layers.
    Type: Application
    Filed: May 5, 2023
    Publication date: October 10, 2024
    Applicant: Advanced ACEBIOTEK CO., LTD.
    Inventors: Yi-Ping Lin, Yung-Chou Hsu, Jyh-Chern Chen, Shen-Fu Hsu
  • Publication number: 20240332008
    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-? dielectric layer on the interfacial layer, a dipole layer on the high-? dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-? dielectric layer.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 3, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Geetika Bajaj, Tianyi Huang, Hsin-Jung Yu, Yixiong Yang, Srinivas Gandikota, Chi-Chou Lin, Pei Hsuan Lin
  • Publication number: 20240333415
    Abstract: An optical device includes a first waveguide, ring-shaped waveguides adjacent to the first waveguide, and heaters coupled to the ring-shaped waveguides in one-to-one correspondence. A method includes coupling a first light source with a first wavelength to the first waveguide, increasing electric current through the heaters until a first one of the ring-shaped waveguides resonates, assigning the first one of the ring-shaped waveguides to the first wavelength, resetting the electric current through the heaters to the initial electric current, coupling a second light source with a second wavelength to the first waveguide wherein the second wavelength is different from the first wavelength, increasing the electric current through the heaters until a second one of the ring-shaped waveguides resonates wherein the second one of the ring-shaped waveguides is different from the first one of the ring-shaped waveguides, and assigning the second one of the ring-shaped waveguides to the second wavelength.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Stefan Rusu, Weiwei Song, Lan-Chou Cho
  • Patent number: 12104786
    Abstract: A burner of a gas stove includes a burner body, a partition member, and at least one flame cover. The burner body includes a gas conduit and a base. The gas conduit has at least one gas input passage for injecting gas and air, and the base has at least one mixture passage for mixing the gas and the air. The at least one mixture passage communicates with the at least one gas input passage. The partition member has a plurality of through holes and covers the at least one mixture passage. The at least one flame cover provided with a plurality of flame holes covers the partition member. Whereby, the size of the burner of the gas stove is reduced significantly, and the gas can mix with the air effectively and uniformly.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 1, 2024
    Assignee: GRAND MATE CO., LTD.
    Inventors: Chung-Chin Huang, Chin-Ying Huang, Hsin-Ming Huang, Hsing-Hsiung Huang, Yen-Jen Yeh, Wei-Long Chen, Kuan-Chou Lin, Tang-Yuan Luo
  • Publication number: 20240312980
    Abstract: A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a first doped well doped with a first impurity having a first conductivity type, a second doped well adjacent the first doped well and doped with a second impurity having a second conductivity type opposite the first conductivity type, a third doped well adjacent the second doped well and doped with a third impurity having the first conductivity type, a fourth doped region in the third doped well and doped with a fourth impurity having the second conductivity type, and a deep doped well doped with a fifth impurity having the first conductivity type under a first portion of the second doped well, under the third doped well, and under the fourth doped region.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Inventors: Hung-Chou LIN, Yi-Cheng CHIU, Chen-Chien CHANG, Kang-Tai PENG, Tian Sheng LIN
  • Patent number: 12094770
    Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Min Liu, Ming-Yuan Gao, Ming-Chou Chiang, Shu-Cheng Chin, Huei-Wen Hsieh, Kai-Shiang Kuo, Yen-Chun Lin, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 12095142
    Abstract: A semiconductor package includes a first package having a first side and a second side opposing the first side. The first package comprises a first electronic component and a second electronic component arranged in a side-by-side manner on the second side. A second package is mounted on the first side of the first package. The second package comprises a radiative antenna element. A connector is disposed on the second side.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: September 17, 2024
    Assignee: MEDIATEK INC.
    Inventors: Wen-Chou Wu, Yi-Chieh Lin, Chia-Yu Jin, Hsing-Chih Liu
  • Publication number: 20240303432
    Abstract: There is provided a method for determining text blocks of a PDF text, including: acquiring information of characters of the PDF text; performing an initial division according to gap outliers of the PDF text in a transverse direction and a longitudinal direction, and adding block tags of first text blocks to the information of characters; sequentially processing inaccurate lines and inaccurate words in each first text block according to baselines of characters, character lengths, character spaces and character indexes; performing a baseline arrangement on lines of the PDF text; sequentially comparing two lines to form second text blocks; and sequentially comparing two second text blocks to identify whether to perform a secondary merging and a secondary division.
    Type: Application
    Filed: December 1, 2023
    Publication date: September 12, 2024
    Inventors: SHENG-JUN LU, ZHI-PENG LUO, SHUAI WANG, PO-CHOU SU, WEN-WEI LIN
  • Publication number: 20240296272
    Abstract: A method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Inventors: Pin-Dai SUE, Po-Hsiang HUANG, Fong-Yuan CHANG, Chi-Yu LU, Sheng-Hsiung CHEN, Chin-Chou LIU, Lee-Chung LU, Yen-Hung LIN, Li-Chun TIEN, Yi-Kan CHENG
  • Publication number: 20240284653
    Abstract: A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsin-Cheng LIN, Tao CHOU, Chee-Wee LIU
  • Publication number: 20240284008
    Abstract: A server includes a storage adapted to hold video data of past livestreams; and a generating unit adapted to generate, in response to reception of a viewing request for a past livestream, provision data for the viewing request, the provision data being generated such that, among interactions made in the livestream, output of an interaction that meets a predetermined criterion is restricted.
    Type: Application
    Filed: August 30, 2023
    Publication date: August 22, 2024
    Inventors: Ka Ho FONG, Chou-Keng WU, Yun-An LIN
  • Patent number: 12064754
    Abstract: A titanium catalyst and a synthesizing method of polyester resins are provided in the present disclosure. The titanium catalyst has a chemical structure represented by Formula (I), Formula (II) or Formula (III). The symbols shown in the Formula (I), the Formula (II) or the Formula (III) are defined in the description. The synthesizing method of polyester resins includes providing the titanium catalyst, performing a feeding step, performing a heating and pressurizing step and performing a heating and vacuuming step. The titanium catalyst and a heat stabilizer are added into an autoclave before the feeding step or before the heating and vacuuming step.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: August 20, 2024
    Assignees: NATIONAL TSING HUA UNIVERSITY, CHANG CHUN PLASTICS CO., LTD., CHANG CHUN PETROCHEMICAL CO., LTD., DAIREN CHEMICAL CORP.
    Inventors: Yi-Chou Tsai, John Di Yi Ou, Chuan-Sheng Huang, Yung-Sheng Lin
  • Patent number: 12062545
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Chi-Chou Lin, Kedi Wu, Wen Ting Chen, Shih Chung Chen, Srinivas Gandikota, Mandyam Sriram, Chenfei Shen, Naomi Yoshida, He Ren
  • Patent number: 12062687
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hong-Yang Chen, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
  • Patent number: 12053663
    Abstract: A transmission structure of a climbing machine for an operator to operate in a standing position is disclosed. The transmission structure of the climbing machine includes a base, a support frame, a first slide rail, a second slide rail, a first transmission unit, a second transmission unit, a first handle slider, a first pedal slider, a second handle slider, a second pedal slider, and a resistance unit. The climbing machine is used to train the synchronized and coordinated movements of hands and feet for simulating rock climbing and mountaineering. The support frame, the first slide rail, the second slide rail, the first transmission unit and the second transmission unit are all located at the center line position of the upright trunk of the operator. The volume of the climbing machine can be reduced greatly to save the space occupied.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: August 6, 2024
    Inventor: Tsung-Chou Lin
  • Publication number: 20240243165
    Abstract: A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Tao CHOU, Chee-Wee LIU
  • Patent number: 12039244
    Abstract: The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Jen-Yuan Chang, Jheng-Hong Jiang, Chin-Chou Liu, Long Song Lin
  • Publication number: 20240194744
    Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 13, 2024
    Inventors: Yi-Cheng CHIU, Tian Sheng LIN, Hung-Chou LIN, Yi-Min CHEN, Chiu-Hua CHUNG
  • Publication number: 20240183033
    Abstract: Embodiments of the present disclosure advantageously provide improved control over precursor/reactant pulse/purge time, greater growth per cycle, and higher throughput during formation of a metal-containing film on a substrate surface (including substrate surfaces having at least one feature) compared to traditional atomic layer deposition (ALD) processes. In some embodiments, forming the metal-containing film comprises exposing a substrate to a constant flow of an inert carrier gas and a co-flow of a pulse of a metal-containing precursor and a pulse of a reactant. The pulse of the metal-containing precursor and the pulse of the reactant may be interrupted by a mini purge. The metal-containing precursor and/or the reactant may be charged during the mini purge to avoid precursor/reactant depletion.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Tianyi Huang, Srinivas Gandikota, Yixiong Yang, Elizabeth Mao, Chi-Chou Lin