Patents by Inventor Chou Tsai
Chou Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002776Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.Type: GrantFiled: July 12, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jung-Chou Tsai, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11998613Abstract: The present disclosure provides an immunoconjugate includes an antibody comprising an antigen-binding fragment that specifically binds to an epitope in mesothelin, N-glycan binding domain and an N-glycan; a linker linking to the N-glycan; and a payload A and a payload B conjugated to the linker, respectively; wherein the payload A and the payload B are the same or different. A pharmaceutical composition comprises the immunoconjugate and a method for treating cancer are also provided in the disclosure.Type: GrantFiled: June 4, 2021Date of Patent: June 4, 2024Assignee: DEVELOPMENT CENTER FOR BIOTECHNOLOGYInventors: Shih-Hsien Chuang, Wei-Ting Sun, Ying-Shuan Lailee, Chun-Liang Lai, Wun-Huei Lin, Win-Yin Wei, Shih-Chong Tsai, Cheng-Chou Yu, Chao-Yang Huang
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Patent number: 12002706Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.Type: GrantFiled: July 3, 2023Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
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Patent number: 11942543Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.Type: GrantFiled: June 29, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
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Publication number: 20240095439Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Wei-Yi HU, Chih-Ming CHAO, Jung-Chou TSAI
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Publication number: 20230394219Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: ApplicationFiled: August 10, 2023Publication date: December 7, 2023Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
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Publication number: 20230385522Abstract: A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
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Patent number: 11790151Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: GrantFiled: August 10, 2022Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
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Patent number: 11775727Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: GrantFiled: March 12, 2019Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu, Jung-Chou Tsai
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Patent number: 11762041Abstract: A connector detecting device for a connector includes a test vehicle, including a plurality of detecting points, to assemble with the connector; and a function module, formed an electrical connection with the test vehicle, configured to determine a conduction status between the connector and the test vehicle according to a loop of the plurality of detecting points and the connector.Type: GrantFiled: April 26, 2022Date of Patent: September 19, 2023Assignee: Wistron CorporationInventors: Chen-Chou Tsai, Chiao-Pin Wang, Guang-Zong Li, Chung-Yu Lai, I-Hsiu Tseng
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Publication number: 20230229067Abstract: A light source fixing assembly includes an optical engine housing, a circuit board, a light emitting element, a flexible circuit board, a fixing element and an abutting element. The circuit board has a bearing surface, a first fixing region and a first conductive bonding region. The first bonding region and the light emitting element are on the bearing surface. The flexible circuit board is between the optical engine housing and the circuit board. The flexible circuit board has a first surface, a second surface opposite to the first surface, and a second fixing region. The second surface has a second bonding region. The fixing element fixes the circuit board and the flexible circuit board onto the optical engine housing. The abutting element abuts against the flexible circuit board and corresponds to the second bonding region, so that the first bonding region is electrically connected to the second bonding region.Type: ApplicationFiled: January 5, 2023Publication date: July 20, 2023Inventors: TUNG-YI KO, YI-CHOU TSAI
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Publication number: 20230213596Abstract: A connector detecting device for a connector includes a test vehicle, including a plurality of detecting points, to assemble with the connector; and a function module, formed an electrical connection with the test vehicle, configured to determine a conduction status between the connector and the test vehicle according to a loop of the plurality of detecting points and the connector.Type: ApplicationFiled: April 26, 2022Publication date: July 6, 2023Applicant: Wistron CorporationInventors: Chen-Chou Tsai, Chiao-Pin Wang, Guang-Zong Li, Chung-Yu Lai, I-Hsiu Tseng
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Publication number: 20230182123Abstract: A titanium catalyst and a synthesizing method of polyester resins are provided in the present disclosure. The titanium catalyst has a chemical structure represented by Formula (I), Formula (II) or Formula (III). The symbols shown in the Formula (I), the Formula (II) or the Formula (III) are defined in the description. The synthesizing method of polyester resins includes providing the titanium catalyst, performing a feeding step, performing a heating and pressurizing step and performing a heating and vacuuming step. The titanium catalyst and a heat stabilizer are added into an autoclave before the feeding step or before the heating and vacuuming step.Type: ApplicationFiled: May 10, 2022Publication date: June 15, 2023Inventors: Yi-Chou TSAI, John Di Yi OU, Chuan-Sheng HUANG, Yung-Sheng LIN
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Publication number: 20230142853Abstract: Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.Type: ApplicationFiled: January 11, 2023Publication date: May 11, 2023Inventors: Wei-Yi HU, Chih-Ming CHAO, Jung-Chou TSAI
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Patent number: 11607116Abstract: The endoscopic device includes a main member having a front slot and a shaft member having a spiral strip selectively running through the slot. The spiral strip is connected to a rotational element whose front end is provided with an optical element. A camera support element is extended from the main member and a camera element is supported by the camera support element. By running the spiral strip through the slot to turn the rotational element and the optical element, a viewing direction of the camera element is altered by the optical element.Type: GrantFiled: September 23, 2020Date of Patent: March 21, 2023Assignee: BROAD PERSPECT BIOMEDICAL TECHNOLOGY CO., LTD.Inventors: Tsang-Chou Tsai, John Huang
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Patent number: 11556691Abstract: Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.Type: GrantFiled: September 17, 2019Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yi Hu, Chih-Ming Chao, Jung-Chou Tsai
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Patent number: 11532580Abstract: An interconnect structure includes a plurality of first pads, a plurality of second pads, a plurality of first conductive lines in a first layer, a plurality of second conductive lines in a second layer, and a plurality of nth conductive lines in an nth layer. The first pads and the second pads respectively are grouped into a first, a second and an nth group. Each of the first pads in first group is connected to one of the second pads in the first group by one of the first conductive lines. Each of the first pads in the second group is connected to one of the second pads in the second group by one of the second conductive lines. Each of the first pads in the nth group is connected to one of the second pads in the nth group by one of the nth conductive lines.Type: GrantFiled: May 26, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jung-Chou Tsai, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu, Yi-Kan Cheng
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Publication number: 20220382957Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
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Publication number: 20220344293Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.Type: ApplicationFiled: July 12, 2022Publication date: October 27, 2022Inventors: JUNG-CHOU TSAI, FONG-YUAN CHANG, PO-HSIANG HUANG, CHIN-CHOU LIU, YI-KAN CHENG
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Patent number: 11404361Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.Type: GrantFiled: November 12, 2020Date of Patent: August 2, 2022Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai