Abstract: A one-shot circuit that includes a fixed-voltage generating module, a clock-shifting module and a logic operation module is provided. The fixed-voltage generating module is operated according to a system voltage to generate a fixed voltage smaller than the system voltage and not varied accordingly. The clock-shifting module includes a delay circuit and at least one first inverter. The delay circuit receives and delays a clock signal to generate a first delayed clock signal. The first inverter is electrically connected to the delay circuit to be operated according to the fixed voltage to receive the first delayed clock signal and generate a second delayed clock signal that is delayed for a predetermined time period relative to the clock signal. The logic operation module receives the clock signal and the second delayed clock signal to perform a logic operation to generate a one-shot signal.

Abstract: The soft-start circuit includes a first charging transistor, a first capacitor, a second charging transistor, a second capacitor and a clamping p-type transistor. The first charging transistor is conducted in response to activating pulses to charge the first capacitor through a first output node such that a first output voltage at the first output node gradually increases. The second charging transistor is conducted in response to the first output voltage to charge the second capacitor through a second output node such that a second output voltage at the second output node gradually increases. The clamping p-type transistor includes a source terminal electrically connected to a clamping node, a drain terminal connected to a ground terminal and a gate electrically connected to the second output node, and is conducted when a voltage at the clamping node exceeds a clamping threshold value to pull low the voltage at the clamping node.

Abstract: The soft-start circuit includes a first charging transistor, a first capacitor, a second charging transistor, a second capacitor and a clamping p-type transistor. The first charging transistor is conducted in response to activating pulses to charge the first capacitor through a first output node such that a first output voltage at the first output node gradually increases. The second charging transistor is conducted in response to the first output voltage to charge the second capacitor through a second output node such that a second output voltage at the second output node gradually increases. The clamping p-type transistor includes a source terminal electrically connected to a clamping node, a drain terminal connected to a ground terminal and a gate electrically connected to the second output node, and is conducted when a voltage at the clamping node exceeds a clamping threshold value to pull low the voltage at the clamping node.

Abstract: A one-shot circuit that includes a fixed-voltage generating module, a clock-shifting module and a logic operation module is provided. The fixed-voltage generating module is operated according to a system voltage to generate a fixed voltage smaller than the system voltage and not varied accordingly. The clock-shifting module includes a delay circuit and at least one first inverter. The delay circuit receives and delays a clock signal to generate a first delayed clock signal. The first inverter is electrically connected to the delay circuit to be operated according to the fixed voltage to receive the first delayed clock signal and generate a second delayed clock signal that is delayed for a predetermined time period relative to the clock signal. The logic operation module receives the clock signal and the second delayed clock signal to perform a logic operation to generate a one-shot signal.

Abstract: A test mode activation circuit that includes a clock signal generating module, a resistor-capacitor circuit, a current generating module, an output capacitor and a comparator is provided. The clock signal generating module generates a clock signal to an input node such that the resistor-capacitor circuit electrically connected to the input node receives the clock signal to generate a triggering signal every predetermined time interval. The current generating module generates a charging current to an output node in response to the triggering signal. The output capacitor receives the charging current from the output node such that an output voltage of the output node gradually increases. The comparator receives the output voltage from the output node and a reference voltage, wherein the comparator compares the output voltage and the reference voltage to generate a test mode activation signal when the output voltage is larger than the reference voltage.

Abstract: An output stage with short-circuit protection includes a power transistor, a detecting module, a disable module, and a driving module. The power transistor is electrically connected between a voltage source and an output node. A gate end of the power transistor is configured to receive a driving signal. The detecting module is configured to detect an output voltage on the output node to determine whether a short-circuit condition occurs, and to provide a detecting signal according to the output voltage on the output node in the short-circuit condition. The disable module is configured to provide a disable signal according to the detecting signal in the short-circuit condition, and operatively stop the disable signal in each cycle period of a clock signal. The driving module is configured to determine whether to generate the driving signal according to the disable signal and the clock signal.

Abstract: An output stage with short-circuit protection includes a power transistor, a detecting module, a disable module, and a driving module. The power transistor is electrically connected between a voltage source and an output node. A gate end of the power transistor is configured to receive a driving signal. The detecting module is configured to detect an output voltage on the output node to determine whether a short-circuit condition occurs, and to provide a detecting signal according to the output voltage on the output node in the short-circuit condition. The disable module is configured to provide a disable signal according to the detecting signal in the short-circuit condition, and operatively stop the disable signal in each cycle period of a clock signal. The driving module is configured to determine whether to generate the driving signal according to the disable signal and the clock signal.

Abstract: An error amplifier and a LED circuit comprising the same are provided. The LED circuit comprises an inductor, a group of LEDs and a power MOS connected to the inductor, an error amplifier and a pulse width modulator controlling the gate of the power MOS according to an error amplifier output. The error amplifier comprises a differential input stage, an output stage having a NMOS, a PMOS and an adjusting current source connected to the gate of the PMOS. During a first operation mode, a control voltage makes the adjusting current source turn on, and during a second operation mode, the control voltage makes the adjusting current source turn off.

Abstract: A buck circuit having a fast transient response mechanism is provided. The buck circuit comprises a high side MOS, a low side MOS, a transient control module and an operation control module. The low side MOS is connected to the high side MOS at a connection point for generating an output voltage to an external load according to an input voltage from the high side MOS. The operation control module controls the operation of the high and the low side MOS according to the output voltage when the external load is in a heavy load state such that the transient control module is disabled. When the external load turns from the heavy load state to a light load state such that the output voltage raises over a predetermined level, the transient control module is enabled to turn on the low side MOS for discharging to pull down the output voltage.

Abstract: An error amplifier and a LED circuit comprising the same are provided. The LED circuit comprises an inductor, a group of LEDs and a power MOS connected to the inductor, an error amplifier and a pulse width modulator controlling the gate of the power MOS according to an error amplifier output. The error amplifier comprises a differential input stage, an output stage having a first NMOS, a first PMOS, a second NMOS, a second PMOS and a control switch module. During a first operation mode, the control switch module connects the first NMOS and PMOS and connects the second NMOS and PMOS, and during a second operation mode, control switch module disables the second NMOS and PMOS.

Abstract: A power-off control circuit adapted in a LCD panel comprising a gate pulse modulator and a level shifter is provided. The power-off control circuit comprises a logic gate and a control switch. The logic gate comprises a first input to receive an internal power supply, a second input to receive a power state signal and a logic output to generate a control signal. When the power supply is on, the internal power supply is on and the power state signal is in a first state to make the control signal turn off the control switch. When the power supply is off, the internal power supply is on and the power state signal is in a second state to make the control signal turn on the control switch to make the gate pulse modulator makes pixels of a pixel array to perform a discharge activity.

Abstract: A LED circuit is provided. The LED circuit comprises: a plurality of LED channels, a driving module and a feedback-selecting module. The driving module supplies a driving voltage to the plurality of LED channels according to a feedback voltage. The feedback-selecting module comprises an open detection unit and a minimum-selecting unit. The open detection unit performs an open detection mechanism to separate the plurality of LED channels into a plurality of open LED channels and a plurality of non-open LED channels having an output voltage respectively. The minimum-selecting unit performs a selection mechanism to select a minimum output voltage as the feedback voltage from the output voltage of each of the plurality of non-open LED channels. A LED circuit operation method adapted in the LED circuit is provided herein as well.

Abstract: A buck circuit having a fast transient response mechanism is provided. The buck circuit comprises a high side MOS, a low side MOS, a transient control module and an operation control module. The low side MOS is connected to the high side MOS at a connection point for generating an output voltage to an external load according to an input voltage from the high side MOS. The operation control module controls the operation of the high and the low side MOS according to the output voltage when the external load is in a heavy load state such that the transient control module is disabled. When the external load turns from the heavy load state to a light load state such that the output voltage raises over a predetermined level, the transient control module is enabled to turn on the low side MOS for discharging to pull down the output voltage.

Abstract: A charge pump driving circuit for generating a driving pulse signal to drive a charge pump circuit is disclosed. The charge pump driving circuit includes a control signal generator and a driving signal generator. The control signal generator generates a first control signal, a second control signal, and a third control signal, in which the third control signal transits in the first place, the first control signal transits next, and the second control signal transits last. The driving signal generator, controlled by the first control signal, the second control signal and the third control signal, generates the driving pulse signal, in which the driving signal generator has a rare short circuit current flowing from a supply terminal providing a supply voltage to a ground terminal providing a ground voltage.

Abstract: A LED circuit is provided. The LED circuit comprises: a plurality of LED channels, a driving module and a feedback-selecting module. The driving module supplies a driving voltage to the plurality of LED channels according to a feedback voltage. The feedback-selecting module comprises an open detection unit and a minimum-selecting unit. The open detection unit performs an open detection mechanism to separate the plurality of LED channels into a plurality of open LED channels and a plurality of non-open LED channels having an output voltage respectively. The minimum-selecting unit performs a selection mechanism to select a minimum output voltage as the feedback voltage from the output voltage of each of the plurality of non-open LED channels. A LED circuit operation method adapted in the LED circuit is provided herein as well.

Abstract: An error amplifier and a LED circuit comprising the same are provided. The LED circuit comprises an inductor, a group of LEDs and a power MOS connected to the inductor, an error amplifier and a pulse width modulator controlling the gate of the power MOS according to an error amplifier output. The error amplifier comprises a differential input stage, an output stage having a first NMOS, a first PMOS, a second NMOS, a second PMOS and a control switch module. During a first operation mode, the control switch module connects the first NMOS and PMOS and connects the second NMOS and PMOS, and during a second operation mode, control switch module disables the second NMOS and PMOS.

Abstract: An error amplifier and a LED circuit comprising the same are provided. The LED circuit comprises an inductor, a group of LEDs and a power MOS connected to the inductor, an error amplifier and a pulse width modulator controlling the gate of the power MOS according to an error amplifier output. The error amplifier comprises a differential input stage, an output stage having a NMOS, a PMOS and an adjusting current source connected to the gate of the PMOS. During a first operation mode, a control voltage makes the adjusting current source turn on, and during a second operation mode, the control voltage makes the adjusting current source turn off.

Abstract: A short detection circuit, for detecting an output node corresponding to an output voltage converted from an input voltage of a power converter, includes a first current source, a charging/discharging unit, a comparator, and a logic control unit. The charging/discharging unit performs charging operation in accordance with the first current source to generate a charging signal in a shorted condition of the output node. The comparator outputs an enable signal by comparing the charging signal with a reference signal. The logic control unit is controlled by the enable signal to generate a fault signal for turning off a first switch coupled between the output node and the input voltage in the shorted condition of the output node. A method for detecting short of an output node corresponding to an output voltage converted from an input voltage of a power converter is also disclosed herein.

Abstract: A voltage converter to convert a high voltage to a low voltage is provided. The voltage converter comprises: a current mirror, a current bias, a plurality of loads and a low voltage output. The current mirror comprises a first PMOS and a second PMOS, wherein the source of the first PMOS and the second PMOS receive a high voltage input which is a supply voltage of the current mirror, and the gate of the first PMOS is connected to the drain of the first PMOS. The current bias is connected between the drain of the first PMOS and a ground potential. The plurality of loads are parallel connected between the drain of the second PMOS and the ground potential. And the low voltage output connected to the drain of the second PMOS.

Abstract: A charge pump driving circuit for generating a driving pulse signal to drive a charge pump circuit is disclosed. The charge pump driving circuit includes a control signal generator and a driving signal generator. The control signal generator generates a first control signal, a second control signal, and a third control signal, in which the third control signal transits in the first place, the first control signal transits next, and the second control signal transits last. The driving signal generator, controlled by the first control signal, the second control signal and the third control signal, generates the driving pulse signal, in which the driving signal generator has a rare short circuit current flowing from a supply terminal providing a supply voltage to a ground terminal providing a ground voltage.