Abstract: A processor is provided with a register file comprising a plurality of vector registers, and an execution core coupled to the register file, where the execution core is configured to execute a set of checksum instructions with a first checksum instruction to specify a first vector operand, a second vector operand, and a result vector operand, where the first vector operand is in a first vector register of the plurality of vector registers, the second vector operand is in a second register of the plurality of vector registers, and the result vector operand is to be written to a third vector register of the plurality of vector registers, and to execute the first checksum instruction, the execution core is configured to accumulate bytes from the first vector operand and the second vector operand into a first portion of the result vector operand and add the accumulated bytes from the first vector operand and the second vector operand to a second portion of the result vector operand to generate the second portion

Abstract: A processor is provided with a register file comprising a plurality of vector registers, and an execution core coupled to the register file, where the execution core is configured to execute a set of checksum instructions with a first checksum instruction to specify a first vector operand, a second vector operand, and a result vector operand, where the first vector operand is in a first vector register of the plurality of vector registers, the second vector operand is in a second register of the plurality of vector registers, and the result vector operand is to be written to a third vector register of the plurality of vector registers, and to execute the first checksum instruction, the execution core is configured to accumulate bytes from the first vector operand and the second vector operand into a first portion of the result vector operand and add the accumulated bytes from the first vector operand and the second vector operand to a second portion of the result vector operand to generate the second portion

Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing. A compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

Abstract: An FM audio receiver can include a mono/stereo detector that causes the audio receiver to output either a monophonic or a stereophonic signal based on a received pilot tone energy. An accurate operation of the receiver, including but not limited to correct decoding of monophonic/stereophonic reception, can be based on the receiver operating with the same rated maximum system deviation (RMSD) as the received signal itself. Aspects of the disclosure describe a system and method of detecting and matching a receiver's RMSD to that of a received signal by demodulating a carrier bearing a an input signal over a first bandwidth, extracting a pilot energy signal from the input signal, and demodulating the carrier bearing the input signal over a second bandwidth if the pilot energy signal is within a pilot energy range for a first predetermined amount of time.

Abstract: An audio receiver may include a mono/stereo detector that causes the audio receiver to output either a monophonic or a stereophonic signal based on a difference between a pilot energy signal and a filtered pilot energy signal. The audio receiver includes a filter that filters the pilot energy signal to generate a filtered pilot energy signal, wherein a variable leakage factor associated with the filter is used to minimize a noise level of the filtered pilot energy signal and to reduce a response time of the audio receiver.

Abstract: Methods and apparatus are provided for receiving a first signal and generating an output signal indicative of radio data system (“RDS”) information. A receiver circuit of the invention can include mixer circuitry, lowpass filter circuitry, downsampler circuitry, and decoder circuitry. Advantageously, the receiver circuit can operate entirely within the digital domain, promoting interoperability with digital frequency modulation (“FM”) demodulator circuitry.

Abstract: A system and method for switching a mode of a receiver between a monophonic and stereophonic mode is disclosed. The method can include generating a residual signal indicative of a noise level associated with a pilot energy signal, calculating a residual block energy level of the residual signal over an observation interval, generating a monitor signal based on a number of times the pilot energy signal is less than a pilot energy threshold during the observation interval and switching the mode of the receiver based on the residual block energy level and the monitor signal.

Abstract: A receiver may estimate a channel condition based on a difference between a pilot energy signal and a filtered pilot energy signal. The receiver may further switch to a stereophonic mode when both the difference and an energy level of the pilot energy signal satisfy a predetermined requirement of the receiver, and switch to a monophonic mode when either the difference or the energy level of the pilot energy signal fail to satisfy the predetermined requirement of the receiver.

Abstract: An audio receiver may include a mono/stereo detector that causes the audio receiver to output either a monophonic or a stereophonic signal based on a difference between a pilot energy signal and a filtered pilot energy signal. The audio receiver includes a filter that filters the pilot energy signal to generate a filtered pilot energy signal, wherein a variable leakage factor associated with the filter is used to minimize a noise level of the filtered pilot energy signal and to reduce a response time of the audio receiver.

Abstract: Disclosed herein are systems and methods for accurate removal of I/Q mismatch in received signals of an analog FM receiver. The analog FM receiver includes a down-converter, a calibration circuit that estimates I/Q mismatch values, and a compensation circuit that uses the estimated mismatch values to reduce the effects of I/Q mismatch. In one aspect, the calibration circuit uses an adaptive dual-parameter compensation scheme to iteratively correct the received signals by approximating a coefficient value and an amplitude value that minimize the signals' amplitude variation from the amplitude value. In another aspect, phase and amplitude mismatch parameters can be determined using the coefficient value.

Abstract: Methods and apparatus are provided for receiving a first signal and generating an output signal indicative of radio data system (“RDS”) information. A receiver circuit of the invention can include mixer circuitry, lowpass filter circuitry, downsampler circuitry, and decoder circuitry. Advantageously, the receiver circuit can operate entirely within the digital domain, promoting interoperability with digital frequency modulation (“FM”) demodulator circuitry.

Abstract: Disclosed herein are systems and methods for recovering a sub-carrier signal from a multiplexed signal having an embedded pilot tone signal. The recovery system includes circuitry for recovering a pilot signal from the received multiplexed signal, for generating a frequency-doubled signal from the recovered pilot signal, and for phase-shifting the frequency-doubled signal by a pre-determined phase difference from the embedded pilot tone signal. Another recovery system includes circuitry for recovering a pilot signal from the received multiplexed signal, for phase-shifting the pilot signal by a pre-determined phase difference from the embedded pilot tone signal, and for generating a frequency-doubled signal from the phase-shifted signal.

Abstract: Methods and apparatus are provided for receiving a first signal and generating an output signal indicative of radio data system (“RDS”) information. A receiver circuit of the invention can include mixer circuitry, lowpass filter circuitry, downsampler circuitry, and decoder circuitry. Advantageously, the receiver circuit can operate entirely within the digital domain, promoting interoperability with digital frequency modulation (“FM”) demodulator circuitry.

Abstract: An FM audio receiver can include a mono/stereo detector that causes the audio receiver to output either a monophonic or a stereophonic signal based on a received pilot tone energy. An accurate operation of the receiver, including but not limited to correct decoding of monophonic/stereophonic reception, can be based on the receiver operating with the same rated maximum system deviation (RMSD) as the received signal itself. Aspects of the disclosure describe a system and method of detecting and matching a receiver's RMSD to that of a received signal by demodulating a carrier bearing a an input signal over a first bandwidth, extracting a pilot energy signal from the input signal, and demodulating the carrier bearing the input signal over a second bandwidth if the pilot energy signal is within a pilot energy range for a first predetermined amount of time.

Abstract: Disclosed herein are systems and methods for recovering a sub-carrier signal from a multiplexed signal having an embedded pilot tone signal. The recovery system includes circuitry for recovering a pilot signal from the received multiplexed signal, for generating a frequency-doubled signal from the recovered pilot signal, and for phase-shifting the frequency-doubled signal by a pre-determined phase difference from the embedded pilot tone signal. Another recovery system includes circuitry for recovering a pilot signal from the received multiplexed signal, for phase-shifting the pilot signal by a pre-determined phase difference from the embedded pilot tone signal, and for generating a frequency-doubled signal from the phase-shifted signal.

Abstract: A receiver may estimate a channel condition based on a difference between a pilot energy signal and a filtered pilot energy signal. The receiver may further switch to a stereophonic mode when both the difference and an energy level of the pilot energy signal satisfy a predetermined requirement of the receiver, and switch to a monophonic mode when either the difference or the energy level of the pilot energy signal fail to satisfy the predetermined requirement of the receiver.

Abstract: A system and method for switching a mode of a receiver between a monophonic and stereophonic mode is disclosed. The method can include generating a residual signal indicative of a noise level associated with a pilot energy signal, calculating a residual block energy level of the residual signal over an observation interval, generating a monitor signal based on a number of times the pilot energy signal is less than a pilot energy threshold during the observation interval and switching the mode of the receiver based on the residual block energy level and the monitor signal.