Abstract: An improved capacitor is provided wherein the capacitor has an improved bond between the anode and anode wire. The anode comprises a pressed anode powder comprising a first density region and a second density region wherein the second density region has a higher density than the first density region. An anode wire extends into the second density region wherein the anode wire in the second density region is distorted by compression. This allows for better utilization of the metal powder surface area by allowing a lower bulk press density and lower sinter temperature while still achieving the necessary wire pull strength. In addition, this invention when utilized with deoxidation steps, results in sufficient wire pull strengths not possible otherwise.

Abstract: Various techniques are disclosed for providing a radar system. In one example, such a radar system includes a radar unit adapted to broadcast radar signals and receive return signals in response thereto. The radar unit includes a waveform generator adapted to provide pulse waveforms of different pulse widths and Frequency Modulated Continuous Wave (FMCW) waveforms, wherein the waveforms are interleaved with each other to provide a transmission sequence for the radar signals for detection of long range and short range targets, a power amplifier adapted to amplify the radar signals for broadcast, and an antenna adapted to broadcast the radar signals and receive the return signals. Other examples of radar systems and related methods are also provided.

Abstract: Various techniques are disclosed for providing a radar system. In one example, such a radar system includes a radar unit adapted to broadcast radar signals and receive return signals in response thereto. The radar unit includes a waveform generator adapted to provide pulse waveforms of different pulse widths and Frequency Modulated Continuous Wave (FMCW) waveforms, wherein the waveforms are interleaved with each other to provide a transmission sequence for the radar signals for detection of long range and short range targets, a power amplifier adapted to amplify the radar signals for broadcast, and an antenna adapted to broadcast the radar signals and receive the return signals. Other examples of radar systems and related methods are also provided.

Abstract: Various techniques are disclosed for providing a radar system. In one example, such a radar system includes a radar unit adapted to broadcast radar signals and receive return signals in response thereto. The radar unit includes a waveform generator adapted to provide pulse waveforms of different pulse widths and Frequency Modulated Continuous Wave (FMCW) waveforms, wherein the waveforms are interleaved with each other to provide a transmission sequence for the radar signals for detection of long range and short range targets, a power amplifier adapted to amplify the radar signals for broadcast, and an antenna adapted to broadcast the radar signals and receive the return signals. Other examples of radar systems and related methods are also provided.

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract: Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.

Abstract: Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, a serial presence detect function is included within a memory module buffer instead of being provided by a separate EEPROM device mounted on the memory module. Various embodiments thus can provide cost savings, chip placement and signal routing simplification, and can in some circumstances save pins on the module. Other embodiments are described and claimed.

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

Abstract: Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Abstract: Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Abstract: Implementing termination on a bus. According to one embodiment of the present invention a driver drives a default signal on to a line, then drives an information signal on to the line, and then drives the default signal on to the line after driving the information signal on to the line.